Prof. Mary Jane Irwin's visit

We hosted Distinguished Lecture Series, sponsored by Computer Research Association's Committee on the Status of Women in Computing Research (CRA-W), Fall 2007.

Prof. Porod's Visit

Prof. Wolfgang Porod visits our fabrication lab.

Mcnight scholarship

Javier Pulecio receives McKnight Foundation Scholarship

Invited Talk sponsored by IEEE@WIE

Dr. Sanjukta Bhanja delivers Invited talk on "Field-Coupled Nano-Computing" for National Symposium on Emerging Computing, IEEE WIE, Kolkata, 2007.

DASS Award

Karthikeyan Lingasubramanian attends Design Automation Summer School 2007.

NSF CAREER Award

Dr. Bhanja receives NSF CAREER award 2007.

Test, Defect Tolerance and Reliability for Emerging Nanotechnologies

S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi, “QCA Circuits for Robust Coplanar Crossing”, in “Test, Defect Tolerance and Reliability for Emerging Nanotechnologies”, edited by Mohammad Tehranipoor, Springer Science +Business Media, LLC.

Tau Beta Pi Outstanding Research Faculty award

Dr. Bhanja receives 2007 Tau Beta Pi Outstanding Engineering Faculty Researcher award

NCRG members receive Provost's nomination of outstanding teaching assistants

Saket Srivastava and Karthikeyan Lingasubramanian receives nomination for Provost's Oustanding Teaching Assistant award, 2007

Probabilistic error modeling for sequential logic

@INPROCEEDINGS{4601266,
title={Probabilistic error modeling for sequential logic},
author={Lingasubramanian, K. and Bhanja, S.},
booktitle={Nanotechnology, 2007. IEEE-NANO 2007. 7th IEEE Conference on},
year={2007},
month={Aug.},
volume={},
number={},
pages={616-620},
abstract={Reliability is a crucial issue in nanoscale devices including both CMOS (beyond 22 nm) and non-CMOS. Devices in this regime tend to be more prone to errors due to thermal effects creating uncertainty in device characteristics. The transient nature of these errors commands the need for a probabilistic model that can represent the inherent circuit logic and can measure the errors. In sequential logic the error occurred in a particular time frame will be propagated to consecutive time frames thereby making the device more volatile. Any model that can represent a sequential logic should handle both spatial dependencies between nodes in a single time slice and temporal dependencies between nodes of different time slices. While modeling error in sequential logic the complexity arises in handling the temporal dependencies due to the feedback. Essentially, the feedback makes the system non-causal where outputs depend not only on inputs but also its own previous values. Depending on the circuit structure and the nature of feedback, various circuits would offer different degree of temporal dependence. In this work we propose a probabilistic error model for sequential logic that can measure the average output error probability that account for the spatio-temporal nature of the inherent dependencies using an temporally evolving causal Bayesian Networks also called Dynamic Bayesian Networks.},
keywords={CMOS logic circuits, belief networks, integrated circuit reliability, nanotechnology, probability, sequential circuits, thermal stabilityCMOS integrated circuit, average output error probability, dynamic Bayesian networks, inherent circuit logic, nanoscale devices, probabilistic error modeling, reliability, sequential logic, thermal effects},
doi={10.1109/NANO.2007.4601266},
ISSN={}, }

Reliability of Bi-stable Single Domain Nano Magnets for Cellular Automata

J. Pulecio and S. Bhanja, “Reliability of Bi-stable Single Domain Nano Magnets for Cellular Automata”, Accepted for publication in IEEE conference on nanotechnology, Hong Kong, 2007. (Note: Accepted Extended Summaries will be published in the IEEE Review of Advances on Micro, Nano, and Molecular Systems)

@INPROCEEDINGS{4601302,
title={Reliability of bi-stable single domain nano magnets for Cellular Automata},
author={Pulecio, J.F. and Bhanja, S.},
booktitle={Nanotechnology, 2007. IEEE-NANO 2007. 7th IEEE Conference on},
year={2007},
month={Aug.},
volume={},
number={},
pages={782-786},
abstract={Quantum cellular automata, also known as QCA, has been touted as a pragmatic use of quantum phenomena which currently are detrimental in nano-transistor technology. Recently, QCA technologies has expanded into magnetism, an area referred to as magnetic QCA, by exploiting the magnetic coupling interaction between neighboring cells (nano-magnets). The interactions of orderly fabricated nano-magnets and the viability of nano-magnetic structures as logical building blocks has yet to be explored in great detail. We have fabricated nano-scale magnetic QCA cells and currently the scope entails determining how factors such as material, size, placement, and surface roughness affect the magnetic properties and coupling interactions between the nano- magnetic QCA cells.},
keywords={cellular automata, logic devices, magnetic devices, nanostructured materials, nanotechnology, reliability, surface roughnessbi-stable single domain nanomagnets, nanomagnetic QCA cells, nanomagnetic structures, nanotransistor technology, quantum cellular automata, surface roughness},
doi={10.1109/NANO.2007.4601302},
ISSN={}, }

Probabilistic Maximum Error Modeling for Unreliable Logic Circuits

K. Lingasubramanian and S.Bhanja, “Probabilistic Maximum Error Modeling for Unreliable Logic Circuits”, Accepted for publication in ACM Great Lake Symposium on VLSI, 2007.

@conference{lingasubramanian2007probabilistic,
title={{Probabilistic maximum error modeling for unreliable logic circuits}},
author={Lingasubramanian, K. and Bhanja, S.},
booktitle={Proceedings of the 17th ACM Great Lakes symposium on VLSI},
pages={223--226},
year={2007},
organization={ACM New York, NY, USA}
}

QCA Circuits for Robust Coplanar Crossing

S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi, “QCA Circuits for Robust Coplanar Crossing”, Accepted in, Journal of Electronic Testing: Theory and Applications (JETTA), Volume 23, Issue 2, pp. 193-210, 2007.

@article{bhanja2007qca,
title={{QCA circuits for robust coplanar crossing}},
author={Bhanja, S. and Ottavi, M. and Lombardi, F. and Pontarelli, S.},
journal={Journal of Electronic Testing},
volume={23},
number={2},
pages={193--210},
year={2007},
publisher={Springer}
}

Hierarchical Probabilistic Macromodeling for QCA Circuits

S. Srivastava and S. Bhanja, “Hierarchical Probabilistic Macromodeling for QCA Circuits”, in special issue of Nano Systems and Computing, IEEE Transactions on Computers, Volume56, Issue 2, pp. 174 – 190, 2007.

@ARTICLE{4042678,
title={Hierarchical Probabilistic Macromodeling for QCA Circuits},
author={Saket Srivastava and Sanjukta Bhanja},
journal={Computers, IEEE Transactions on},
year={2007},
month={Feb. },
volume={56},
number={2},
pages={174-190},
abstract={With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, we propose probabilistic macromodels for standard QCA circuit elements based on conditional probability characterization, defined over the output states given the input states. Any circuit model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate three uses for these macromodel-based circuits. First, the probabilistic macromodels allow us to model the logical function of QCA circuits at an abstract level - the "circuit" level - above the current practice of layout level in a time and space efficient manner. We show that the circuit level model is orders of magnitude faster and requires less space than layout level models, making the design and testing of large QCA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Second, the probabilistic macromodels abstract crucial device level characteristics such as polarization and low-energy error state configurations at the circuit level. We demonstrate how this macromodel-based circuit level representation can be used to infer the ground state probabilities, i.e., cell polarizations, a crucial QCA parameter. This allows us to study the thermal behavior of QCA circuits at a higher level of abstraction. Third, we demonstrate the use of these macromodels for error analysis. We show that low-energy state configurations of the macromodel circuit match those of the layout level, thus allowing us to isolate weak p- oints in circuits design at the circuit level itself},
keywords={cellular automata, integrated circuit modelling, probability, quantum computing, semiconductor quantum dotsBayesian network, QCA circuits, circuit thermal behavior, conditional probability characterization, error analysis, ground state probability inference, hierarchical probabilistic macromodeling, joint probability distribution, logic element macromodels, macromodel-based circuit level representation, quantum-dot cellular automata},
doi={10.1109/TC.2007.30},
ISSN={0018-9340}, }

Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps

S. Srivastava and S. Bhanja, "Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps", accepted for publication in IEEE/ACM Intl. Conf. on Microelectronic Systems Education (MSE), 2007.

WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course

S. Srivastava and S. Bhanja, “WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2007.

Dr. Alam (Freescale Semiconductors) delivers Invited Colloquium

Dr. Syed Alam delivers Invited Colloquium talk on 3-Dimensional Integrated Cirsuit, Summer 2007.