Education-related Publications (Journal and Conference)

1.      A. Hoque, W. Sutton, K. A. Roxy and S. Bhanja, "Integrating emerging memory technologies into undergraduate logic design course: The impact of context based teaching," 2017 IEEE International Conference on Microelectronic Systems Education (MSE), Lake Louise, AB, 2017, pp. 31-34.

2.      J. Das, and S. Bhanja, “A Novel Knowledge Module to Integrate Threshold Logic and Post-CMOS Technology into Undergraduate Logic Design Classroom" in IEEE Interdisciplinary Engineering Education Conference (IEDEC), pp. 24-30, March 2014.

3.      C. Siyambalapitiya, R. Hyde, K. Kusmierek  and S.Bhanja, “Effectiveness of Knowledge Module on “Intel 45 nm Transistor and High-k Dielectric”
into Undergraduate Semiconductor Devices Course”, in IEEE 2^nd Interdisciplinary Engineering Design Education Conference (IEDEC),  pp. 83 – 87, 2011.

4.       D. Karunaratne, S. Rajaram, P. De, K. Kusmierek  and S. Bhanja, “Novel knowledge module on fusion of logic and memory to undergraduate students”, in IEEE Microelectronic System Education Conference, pp. 64-67, 2011.

5.        J. Pulecio, A. Pulecio, M. Westlake and S. Bhanja, “A Snapshot of Young America’s Perspective towards STEM”, in IEEE Frontiers in Education (FIE),  pp. S2E-1 – S2E-2, 2010.

6.        K. Lingasubramanian and S. Bhanja, " Work In Progress - An Education Module on Engineering Ethics Concentrating on Environment-Friendly Engineering for Computer Engineers", in IEEE Frontiers in Education (FIE),  pp.  903-904, 2009.

7.        A. Kumari and S. Bhanja, "CNT logic knowledge module integrated in digital CMOS logic design", in IEEE Microelectronics Semiconductor Education,  pp. 115-117, 2009.

8.        S. Srivastava and S. Bhanja, “Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course”, in IEEE Transactions on Education, vol. 51(3), pp. 349-355, 2008.

9.        S. Srivastava and S. Bhanja, “WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course”, in 37^th ASEE/IEEE Frontiers in Education (FIE), pp. S1C, 2007.

10.     S. Srivastava and S. Bhanja, "Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps", in IEEE/ACM Intl. Conference on Microelectronic Systems Education (MSE), pp. 55-56, 2007.

11.     S. Bhanja, “WIP: Enhancing Performance using Dominant Sensory Mode in Co-opeartive Learning Environment for VLSI Design Courses”, IEEE Frontiers in  Education (FIE), pp. 14-15, October, 2007.

Effectiveness of Knowledge Module on “Intel 45 nm Transistor and High-k Dielectric” into Undergraduate Semiconductor Devices Course (IEEE IEDEC 2012)

C. Siyambalapitiya, R. Hyde, K. Kusmierek and S.Bhanja, “Effectiveness of Knowledge
Module on “Intel 45 nm Transistor and High-k Dielectric” into Undergraduate Semiconductor
Devices Course”, Accepted for IEEE 2nd Interdisciplinary Engineering Design Education Conference
(IEDEC), 2011.

Novel knowledge module on fusion of logic and memory to undergraduate students (IEEE MSE)

D. Karunaratne, S. Rajaram, P. De, K. Kusmierek and S. Bhanja, “Novel knowledge module on fusion of logic and memory to undergraduate students”, to IEEE Microelectronic System Education Conference, 2011.

A Snapshot of Young America's Perspective Towards STEM

J. Pulecio, A. pulecio, M. Westlake and S. Bhanja, “A Snapshot of Young America's Perspective Towards STEM”, ASEE/IEEE Frontiers in Education (FIE), 2010.

Work In Progress - An Education Module on Engineering Ethics Concentrating on Environment-Friendly Engineering for Computer Engineers

K. Lingasubramanian and S. Bhanja, " Work In Progress - An Education Module on Engineering Ethics Concentrating on Environment-Friendly Engineering for Computer Engineers", Accepted for publication in IEEE Frontiers in Education (FIE), 2009

CNT logic knowledge module integrated in digital CMOS logic design

A. Kumari and S. Bhanja, "CNT logic knowledge module integrated in digital CMOS logic design", IEEE Microelectronics Semiconductor Education, 2009

Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course

S. Srivastava and S. Bhanja, “Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course”, Accepted for publication in IEEE Transactions on Education, 2008.

@ARTICLE{4569869,
title={Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course},
author={Srivastava, S. and Bhanja, S.},
journal={Education, IEEE Transactions on},
year={2008},
month={Aug. },
volume={51},
number={3},
pages={349-355},
abstract={ This work discusses a knowledge module in an undergraduate logic design course for electrical engineering (EE) and computer science (CS) students, that introduces them to nanocomputing concepts. This knowledge module has a twofold objective. First, the module interests students in the fundamental logical behavior and functionality of the nanodevices of the future, which will motivate them to enroll in other elective courses related to nanotechnology, offered in most EE and CS departments. Second, this module can be used to let students analyze, synthesize, and apply their existing knowledge of the Karnaugh-map-based Boolean logic reduction scheme into a revolutionary design context with majority logic. Where many efforts focus on developing new courses on nanofabrication and even nanocomputing, this work is designed to augment the existing standard EE and CS courses by inserting knowledge modules on nanologic structures so as to stimulate student interest without creating a significant diversion from the course framework. },
keywords={Boolean functions, computer science education, electrical engineering education, logic design, nanoelectronicsKarnaugh-map-based Boolean logic reduction scheme, computer science students, electrical engineering students, nanocomputing concepts, nanodevices, nanofabrication, nanologic knowledge module, revolutionary design, undergraduate logic design course},
doi={10.1109/TE.2008.919660},
ISSN={0018-9359}, }

Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps

S. Srivastava and S. Bhanja, "Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps", accepted for publication in IEEE/ACM Intl. Conf. on Microelectronic Systems Education (MSE), 2007.

WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course

S. Srivastava and S. Bhanja, “WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2007.

WIP- Dominant Sensory Mode based Groups in VLSI Classes

S. Bhanja, “WIP- Dominant Sensory Mode based Groups in VLSI Classes”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2006.

@conference{bhanja2006work,
title={{Work in Progress: Dominant Sensory Mode based Groups in VLSI Classes}},
author={Bhanja, S.},
booktitle={Frontiers in Education Conference, 36th Annual},
pages={14--15},
year={2006}
}

Abstract:


This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class. Our motivation is to make our students aware of fundamental abstracted logical behaviors of future nano-devices, their functionality. This effort would also help the students use their existing knowledge of K-map based logical synthesis into constructing logic blocks for novel devices that uses majority logic as basic construct. Moreover, additional to stimulating our students' interests, we are also augmenting their learning by challenging them to use their existing knowledge to analyze, synthesize and comprehend novel nano-logic issues through the worksheets and lecture modules. Whereas many efforts are focusing on developing new courses on nanofabrication and even nano-computing, we intend to augment the existing standard EE and CS courses by inserting knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework.