Direct Quadratic Minimization Using Magnetic Field-Based Computing

Direct Quadratic Minimization Using Magnetic Field-Based Computing Sarkar, S. Bhanja, S. Dept. of Comput. Sci. & Eng., South Univ., Tampa, FL This paper appears in: Design and Test of Nano Devices, Circuits and Systems, 2008 IEEE International Workshop on Publication Date: 29-30 Sept. 2008 On page(s): 31 - 34 Location: Cambridge, MA ISBN: 978-0-7695-3379-7 Digital Object Identifier: 10.1109/NDCS.2008.13 Current Version Published: 2008-10-03

Abstract We explore an unconventional front in computing,which we call magnetic field-based computing (MFC), that harnesses the energy minimization aspects of a collection of nanomagnets to solve directly quadratic energy minimization problems, such as those arising in computationaolly intensive computer vision tasks. The Hamiltonian of a collection of bipolar nanomagnets is governed by the pairwise dipolar interactions.The ground state of a nanomagnet collection minimizes this Hamiltonian. We have devised a computational method, based on multi-dimensional scaling, to decide upon the spatial arrangement of nanomagnets that matches a particular quadratic minimization problem. Each variable is represented by a nanomagnet and the distances between them are such that the dipolar interactions match the corresponding pairwise energy term in the original optimization problem. We select the nanomagnets that participate in a specific computation from a field of regularly placed nanomagnets. The nanomagnets that do not participate are deselected using transverse magnetic fields. We demonstrate these ideas by solving Landau-Lifshitz equations as implemented in the NISTpsilas micro-magnetic OOMMF software.

Index Terms

Technical Program Co-chair

Dr. Bhanja was selected as Technical Program Co-Chair ACM Great Lakes Symposium on VLSI, 2008

Outstanding Faculty Researcher award

Dr. Bhanja receives University of South Florida “Outstanding Faculty Research Achievement Award”, 2008.

PASI

Javier Pulecio receives Pan American Science Institute scholarship

DSRC Invited Speaker

Dr. Bhanja delivers Invited talk sponsored by DSRC workshop held at Stanford University.

Sloan Fellowship

Javier Pulecio receives Alfred P Sloan fellowship

Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits

A. Shareef, K. Lingasubramanian and S. Bhanja, “Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits”, Accepted for publication in IEEE conference on nanotechnology, Arlington, 2008.

@INPROCEEDINGS{4617250,
title={Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits},
author={Shareef, A. and Lingasubramanian, K. and Bhanja, S.},
booktitle={Nanotechnology, 2008. NANO '08. 8th IEEE Conference on},
year={2008},
month={Aug.},
volume={},
number={},
pages={895-898},
abstract={Devices in nano-regime have inherent propensity for errors due to their very stochastic nature there by making Reliability modeling and evaluation as one of the major issues. To account for these issues, probabilistic models would be more appropriate than deterministic models as they can represent the transient nature of the nano-devices perfectly. In this work, we have used a probabilistic model to study the erroneous behavior of digital logic circuits. Inference on this probabilistic model is performed using junction tree algorithm. Using the unique feature of the junction tree, namely backtracking or Two phase propagation of evidence, we were able to rank or select a subset of input instantiations which are more likely to aggregate error at the output for any given circuit. Using these results we have performed a temporal redundancy scheme using triple temporal redundancy (TTR). As safety- centric designs need worst case behavior study, we have focused on both worst case and average behavior. We have also performed a spatial redundancy scheme using cascaded triple modular redundancy (CTMR) [9], and evaluated the results with those of the temporal redundancy scheme with respect to standard ISCAS'85 benchmark circuits and suggested the best error mitigation scheme for both average and maximum case. Experimental results show that spatial redundancy scheme, irrespective of technique used, is effective in mitigating average output error. Where as Temporal redundancy scheme has out- weighted spatial redundancy scheme in mitigating maximum error.},
keywords={backtracking, benchmark testing, fault trees, nanoelectronics, redundancyISCAS'85 benchmark circuits, backtracking, cascaded triple modular redundancy, digital logic circuits, error mitigation scheme, junction tree algorithm, nanoelectronic circuits, probabilistic model, reliability enhancement, reliability modeling, safety-centric designs, spatial redundancy scheme, temporal redundancy scheme, triple temporal redundancy, two phase propagation of evidence},
doi={10.1109/NANO.2008.268},
ISSN={}, }

Error-Power Tradeoffs in QCA Design

S. Srivastava, S. Sarkar and S. Bhanja, “Error-Power Tradeoffs in QCA Design”, Accepted for publication in IEEE conference on nanotechnology, Arlington, 2008. @INPROCEEDINGS{4617140, title={Error-Power Tradeoffs in QCA Design}, author={Srivastava, S. and Sarkar, S. and Bhanja, S.}, booktitle={Nanotechnology, 2008. NANO '08. 8th IEEE Conference on}, year={2008}, month={Aug.}, volume={}, number={}, pages={530-533}, abstract={In this work we present an error-power tradeoff study in a Quantum-dot Cellular Automata (QCA) circuit design. Device parameter variation to optimize performance is a very crucial step in the development of a technology. In this work we vary the maximum kink energy of a QCA circuit to perform an error-power tradeoff study in QCA design. We make use of graphical probabilistic models to estimate polarization errors and non-adiabatic energy dissipated in a clocked QCA circuit and demonstrate the tradeoff studies on the basic QCA circuits such as majority gate and inverter. We also show how this study can be used by comparing two single bit adder designs. The study will be of great use to designers and fabrication scientists to choose the most optimum size and spacing of QCA cells to fabricate QCA logic designs.}, keywords={cellular automata, logic design, quantum computing, quantum dots, quantum well devicesQCA circuit design, QCA logic design, clocked QCA circuit, error-power tradeoffs, graphical probabilistic model, maximum kink energy, nonadiabatic energy dissipation, polarization errors, quantum-dot cellular automata}, doi={10.1109/NANO.2008.158}, ISSN={}, }

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Thermal Switching Error versus Delay Tradeoffs in Clocked QCA Circuits

S. Bhanja and S. Sarkar, “Thermal Switching Error versus Delay Tradeoffs in Clocked QCA Circuits”, Volume 16, Issue 5, pp. 528 – 541, IEEE Transactions on VLSI Systems, May 2008.

@ARTICLE{4459693,
title={Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits},
author={Bhanja, S. and Sarkar, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2008},
month={May },
volume={16},
number={5},
pages={528-541},
abstract={The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a collection of QCA cells, each with two possible ground states. A four-phased clocking scheme has been suggested to keep the computations at the ground state throughout the circuit. This clocking scheme, however, induces latency or delay in the transmission of information from input to output. In this paper, we study the interplay of computing error behavior with delay or latency of computation induced by the clocking scheme. Computing errors in QCA circuits can arise due to the failure of the clocking scheme to switch portions of the circuit to the ground state with change in input. Some of these non-ground states will result in output errors and some will not. The larger the size of each clocking zone, i.e., the greater the number of cells in each zone, the more the probability of computing errors. However, larger clocking zones imply faster propagation of information from input to output, i.e., reduced delay. Current QCA simulators compute just the ground state configuration of a QCA arrangement. In this paper, we offer an efficient method to compute the N-lowest energy modes of a clocked QCA circuit. We model the QCA cell arrangement in each zone using a graph-based probabilistic model, which is then transformed into a Markov tree structure defined over subsets of QCA cells. This tree structure allows us to compute the N-lowest energy configurations in an efficient manner by local message passing. We analyze the complexity of the model and show it to be polynomial in terms of the number of cells, assuming a finite neighborhood of influence for each QCA cell, which is usually the case. The overall low-energy spectrum of multiple clocking zones is constructed by concatenating the low-energy spectra of the individual clocking zones. We demonstrate how the model can be used to study the tradeoff betwee- n switching errors and clocking zones.},
keywords={cellular automata, clocks, quantum computing, quantum dotsMarkov tree structure, clocked quantum-dot cellular automata circuit, delay tradeoff, four-phased clocking, graph-based probabilistic model, information transmission latency, nano-domain computing architecture, quantum-dot cellular automata model, thermal switching error},
doi={10.1109/TVLSI.2007.915448},
ISSN={1063-8210}, }

Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course

S. Srivastava and S. Bhanja, “Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course”, Accepted for publication in IEEE Transactions on Education, 2008.

@ARTICLE{4569869,
title={Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course},
author={Srivastava, S. and Bhanja, S.},
journal={Education, IEEE Transactions on},
year={2008},
month={Aug. },
volume={51},
number={3},
pages={349-355},
abstract={ This work discusses a knowledge module in an undergraduate logic design course for electrical engineering (EE) and computer science (CS) students, that introduces them to nanocomputing concepts. This knowledge module has a twofold objective. First, the module interests students in the fundamental logical behavior and functionality of the nanodevices of the future, which will motivate them to enroll in other elective courses related to nanotechnology, offered in most EE and CS departments. Second, this module can be used to let students analyze, synthesize, and apply their existing knowledge of the Karnaugh-map-based Boolean logic reduction scheme into a revolutionary design context with majority logic. Where many efforts focus on developing new courses on nanofabrication and even nanocomputing, this work is designed to augment the existing standard EE and CS courses by inserting knowledge modules on nanologic structures so as to stimulate student interest without creating a significant diversion from the course framework. },
keywords={Boolean functions, computer science education, electrical engineering education, logic design, nanoelectronicsKarnaugh-map-based Boolean logic reduction scheme, computer science students, electrical engineering students, nanocomputing concepts, nanodevices, nanofabrication, nanologic knowledge module, revolutionary design, undergraduate logic design course},
doi={10.1109/TE.2008.919660},
ISSN={0018-9359}, }

Sequential Circuit Design in Quantum-Dot Cellular Automata

Sequential Circuit Design in Quantum-Dot Cellular Automata Venkataramani, P. Srivastava, S. Bhanja, S. Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL This paper appears in: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on Publication Date: 18-21 Aug. 2008 On page(s): 534 - 537 Location: Arlington, TX ISBN: 978-1-4244-2103-9 Digital Object Identifier: 10.1109/NANO.2008.159 Current Version Published: 2008-09-03

Abstract In this work we present a novel probabilistic modeling scheme for sequential circuit design in quantum-dot cellular automata(QCA) technology. Clocked QCA circuits possess an inherent direction for flow of information which can be effectively modeled using Bayesian networks (BN). In sequential circuit design this presents a problem due to the presence of feedback cycles since BN are direct acyclic graphs (DAG). The model presented in this work can be constructed from a logic design layout in QCA and is shown to be a dynamic Bayesian Network (DBN). DBN are very powerful in modeling higher order spatial and temporal correlations that are present in most of the sequential circuits. The attractive feature of this graphical probabilistic model is that that it not only makes the dependency relationships amongst node explicit, but it also serves as a computational mechanism for probabilistic inference. We analyze our work by modeling clocked QCA circuits for SR F/F, JK F/F and RAM designs.