Switching activity estimation of VLSI circuits using Bayesian networks

S. Bhanja and N. Ranganathan,“Switching Activity Estimation of VLSI Circuits using Bayesian Networks,” IEEE Transactions on VLSI Systems,
pp. 558- 567, Feb. 2003.


@ARTICLE{1229864,

 title={Switching activity estimation of VLSI circuits using Bayesian networks},
 author={Bhanja, S. and Ranganathan, N.},
 journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
 year={2003},
 month={Aug.},
 volume={11},
 number={4},
 pages={ 558-567},
 abstract={ Switching activity estimation is an important aspect of
power estimation at circuit level. Switching activity in a node is
temporally correlated with its previous value and is spatially
correlated with other nodes in the circuit. It is important to capture
the effects of such correlations while estimating the switching
activity of a circuit. In this paper, we propose a new switching
probability model for combinational circuits that uses a logic-induced
directed-acyclic graph (LIDAG) and prove that such a graph corresponds
to a Bayesian network (BN), which is guaranteed to map all the
dependencies inherent in the circuit. BNs can be used to effectively
model complex conditional dependencies over a set of random variables.
The BN inference schemes serve as a computational mechanism that
transforms the LIDAG into a junction tree of cliques to allow for
probability propagation by local message passing. The proposed approach
is accurate and fast. Switching activity estimation of ISCAS and MCNC
circuits with random and biased input streams yield high accuracy
(average mean error=0.002) and low computational time (average elapsed
time including CPU, memory access and I/O time for the benchmark
circuits=3.93 s).},

keywords={ VLSI, belief networks, directed graphs, integrated
circuit modelling, logic simulation, probability Bayesian network,
Bayesian networks, ISCAS circuits, LIDAG, MCNC circuits, VLSI circuits,
computational mechanism, computational time, conditional dependencies,
junction tree, local message passing, logic-induced directed acyclic
graph, power estimation, probability propagation, switching activity
estimation, switching probability model},

doi={10.1109/TVLSI.2003.816144},
ISSN={1063-8210},
}