Javier Pulecio receives BD Scholarship

Javier Pulecio receives National Science Foundation Bridge to Doctorate scholarship.

Dr. Ottavi's visit

Dr. Marco Ottavi delivers invited lecture on QCA Circuits

DAC YSSP

Javier Pulecio Receives Young Student Support Scholarship to attend DAC 2005

A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC

V. K. Jain, S. Bhanja, G. H. Chapman, L. Doddannagari and N. Nguyen, “A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC”, Accepted for publication for IEEE SOC conference, pp. 243-246, 2005.

@INPROCEEDINGS{1554503,
title={A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC},
author={Jain, V.K. and Bhanja, S. and Chapman, G.H. and Doddannagari, L.},
booktitle={SOC Conference, 2005. Proceedings. IEEE International},
year={2005},
month={Sept.},
volume={},
number={},
pages={ 243-246},
abstract={A 3D heterogeneous system on a chip using a stack of planes has recently been proposed. While the sensors are located on the top plane, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on a reconfigurable computing array for its DSP plane. The advantages of such an approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. The authors presented the reconfigurable J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA_PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the benefits of reduced external interconnect, much reduced design time, and manageable testability. The paper discusses these cells, including a new concept, namely multi-granularity. The methodology for mapping algorithms is illustrated by two important examples, FIR filtering of signals and images and the independent component analysis (ICA) algorithm. Finally, the paper discusses the issue of defect tolerance, which is critical in attaining reasonable yields making chip manufacture feasible.},
keywords={ VLSI, digital signal processing chips, reconfigurable architectures, system-on-chip 3D heterogeneous system-on-chip, DSP plane, coarse grain VLSI cells, data fabric cell, defect tolerance, extended multiply accumulate cell, independent component analysis, reconfigurable J-platform, reconfigurable computing array, universal nonlinear cell},
doi={10.1109/SOCC.2005.1554503},
ISSN={}, }

Scalable Probabilistic Computing Models using Bayesian Networks

T. Rejimon and S. Bhanja, “Scalable Probabilistic Computing Models using Bayesian Networks”, Accepted for IEEE Intl. Midwest Symposium on Circuits and Systems (MWSCAS), pp. 712-715, 2005.

@INPROCEEDINGS{1594200,
title={Scalable probabilistic computing models using Bayesian networks},
author={Rejimon, T. and Bhanja, S.},
booktitle={Circuits and Systems, 2005. 48th Midwest Symposium on},
year={2005},
month={Aug.},
volume={},
number={},
pages={712-715 Vol. 1},
abstract={As technology scales below 100nm and operating frequencies increase, correct operation of nano-CMOS will be compromised due reduced device-to-device distance, imperfections, and low noise and voltage margins. Unlike traditional faults and defects, these errors are expected to be transient in nature. Unlike radiation related upset errors, the propensity of these transient errors will be higher. Due to these highly likely errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic events. We propose the formalism of probabilistic Bayesian networks (BNs), which also forms a complete joint probability model, for probabilistic computing. Using the exact probabilistic inference scheme known as clustering, we show that for a circuit with about 250 gates the output error estimation time is less than three seconds on a 2GHz processor. This is three orders of magnitude faster than a recently proposed method for probabilistic computing using transfer matrices},
keywords={belief networks, errors, logic gates, microcomputers, probabilistic logic, probability, transients2 GHz, Bayesian networks, device-to-device distance, low noise margins, nano-CMOS operation, nanodomain computing, scalable probabilistic computing, transfer matrices, transient errors, voltage margins},
doi={10.1109/MWSCAS.2005.1594200},
ISSN={}, }

Graphical Probabilistic Inference for Ground State and Near-Ground State Computing in QCA Circuits

S. Bhanja and S. Sarkar, “Graphical Probabilistic Inference for Ground State and Near-Ground State Computing in QCA Circuits”, Accepted for publication for IEEE Nanotechnology Conference, pp. 290-293, 2005.

@INPROCEEDINGS{1500753,
title={Graphical probabilistic inference for ground state and near-ground state computing in QCA circuits},
author={Bhanja, S. and Sarkar, S.},
booktitle={Nanotechnology, 2005. 5th IEEE Conference on},
year={2005},
month={July},
volume={},
number={},
pages={ 290-293 vol. 1},
abstract={ We propose a graphical probabilistic Bayesian Network based modeling and inference scheme for Clocked Quantum-dot Cellar Automata (QCA) based circuit design that not only specify just the binary discrete states (0 or 1) of the individual cells, but also the probabilities of observing these states for Ground (Most Likely) state computing. The nodes of the Bayesian Network (BN) are the random variables, representing individual cells, and the links between them capture the dependencies among them. The modeling exploits the spatially local nature of the dependencies and the induced causality from the wave propagation and clocking schemes to arrive at a minimal, factored, representation of the overall joint probability of the cell states in terms of local conditional probabilities. This BN model allows us (1) to estimate the most likely (or ground) state configuration and the next lowest-energy configuration that results in output errors and (2) to show how weak spots in clocked QCA circuit designs can be found using these BN models by comparing the (most likely) ground state configuration with the next most likely energy state configuration that results in output error.},
keywords={ belief networks, cellular automata, ground states, logic circuits, probabilistic automata, quantum computing, quantum dots, wave propagation binary discrete states, cell states, clocked quantum-dot cellar automata based circuit design, clocking schemes, energy state configuration, graphical probabilistic Bayesian network model, graphical probabilistic inference, joint probability, lowest-energy configuration, nanocomputing, near-ground state computing, wave propagation, weak spots},
doi={10.1109/NANO.2005.1500753},
ISSN={ }, }

Synthesizing Energy Minimizing Quantum-dot Cellular Automata Circuits for Vision Computing

S. Sarkar and S. Bhanja, ”Synthesizing Energy Minimizing Quantum-dot Cellular Automata Circuits for Vision Computing”, Accepted for publication for IEEE Nanotechnology Conference, pp. 541-544, 2005.

@INPROCEEDINGS{1500821,
title={Synthesizing energy minimizing quantum-dot cellular automata circuits for vision computing},
author={Sarkar, S. and Bhanja, S.},
booktitle={Nanotechnology, 2005. 5th IEEE Conference on},
year={2005},
month={July},
volume={},
number={},
pages={ 541-544 vol. 2},
abstract={ We harness the energy minimization aspects of the quantum-dot cellular automata (QCA) computing model to synthesize QCA circuits to solve the vision problem of perceptual grouping. Unlike logic computing, vision computing problems are error-tolerant, but are hard to solve on existing computing platforms. The cost of failure of not finding the optimal solution is not high; even solutions that are close to optimal can suffice. The problem of perceptual grouping concerns with selecting, based on Gestaltic perceptual cues, salient subsets of low-level features, such as straight line boundary segments, that are most likely to belong to objects in the scene. We formulate a method to map this problem, which can be cast in terms of energy minimization, onto an arrangement of QCA cells. The QCA cells correspond to the straight lines, and the kink energies between them model the Gestaltic cue affinities. The magnitude of the polarizations of the QCA cells denote the saliency of the corresponding image features. We use classical multi-dimensional scaling (MDS) to synthesize the QCA cell layout. We demonstrate the ability of this arrangement to compute salient groups in real images by simulating the QCA layout using iterative, self consistent analysis, based on the Hartree-Fock approximation.},
keywords={ cellular automata, circuit CAD, computer vision, quantum computing, quantum dots Gestaltic perceptual cues, Hartree-Fock approximation, consistent analysis, iterative analysis, multi-dimensional scaling, quantum-dot cellular automata circuits, vision computing},
doi={10.1109/NANO.2005.1500821},
ISSN={ }, }

Causal Probabilistic Input Dependency Learning for Switching Model in VLSI Circuits

N. Ramalingam and S. Bhanja, “Causal Probabilistic Input Dependency Learning for Switching Model in VLSI Circuits”, Accepted for publication in ACM Great Lake Symposium on VLSI, pp. 112-115, 2005.

@conference{ramalingam2005causal,
title={{Causal probabilistic input dependency learning for switching model in VLSI circuits}},
author={Ramalingam, N. and Bhanja, S.},
booktitle={Proceedings of the 15th ACM Great Lakes symposium on VLSI},
pages={112--115},
year={2005},
organization={ACM New York, NY, USA}
}

Bayesian Modeling of Quantum-dot Cellular Automata Circuits

S. Bhanja and S. Srivastava, “Bayesian Modeling of Quantum-dot Cellular Automata Circuits”, Accepted for publication in Nanotech, National Science and Technology Institute, 2005.

@conference{bhanja2005bayesian,
title={{Bayesian modeling of quantum-dot cellular automata circuits}},
author={Bhanja, S. and Srivastava, S.},
booktitle={NSTI Nanotechnology Conference},
year={2005}
}

A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor

V. Jain, S. Bhanja, G. Chapman, L. Doddannagari and N. Nguyen, “A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor”, Accepted for publication in IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.v77-v80, 2005.


@INPROCEEDINGS{1416244,
title={A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor},
author={Jain, V.K. and Bhanja, S. and Chapman, G.H. and Doddannagari, L. and Nguyen, N.},
booktitle={Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on},
year={2005},
month={March},
volume={5},
number={},
pages={ v/77-v/80 Vol. 5},
abstract={ A 3D heterogeneous sensor using a stacked chip has recently been proposed. While the sensors are located on one of the planes, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on its DSP plane, in particular on the implementation of the ICA (independent component analysis) algorithm in the DSP plane. ICA is a recently proposed method for solving the blind source separation problem. The objective is to recover the unobserved source signals from the observed mixtures without the knowledge of the mixing coefficients. We present a parallel architecture utilizing the reconfigurable J-platform, which employs coarse-gain VLSI cells. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the distinct advantages of reduced external interconnect, much reduced design time, and manageable testability. Additionally, the other algorithms needed for the 3D HSoC can also be mapped on to the same resources, by time multiplexing, thereby reducing the silicon area needed.},
keywords={ VLSI, blind source separation, digital signal processing chips, independent component analysis, parallel architectures, reconfigurable architectures, sensors, system-on-chip 3D HSoC, 3D heterogeneous sensor, ICA algorithm, blind source separation, coarse-gain VLSI cells, data-fabric cell, extended multiply accumulate cell, independent component analysis, parallel architecture, reconfigurable J-platform, sensor DSP plane, stacked chip sensor, time multiplexing, universal nonlinear cell},
doi={10.1109/ICASSP.2005.1416244},
ISSN={1520-6149}, }

An Accurate Probabilistic Model for Error Detection

T. Rejimon and S. Bhanja,” An Accurate Probabilistic Model for Error Detection”, 18th International Conference in VLSI Design, pp.717-722, 2005.


@INPROCEEDINGS{1383359,
title={An accurate probabilistic model for error detection},
author={Rejimon, T. and Bhanja, S.},
booktitle={VLSI Design, 2005. 18th International Conference on},
year={2005},
month={Jan.},
volume={},
number={},
pages={ 717-722},
abstract={We propose a novel single event fault/error model based on logic induced fault encoded directed acyclic graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in nanodomain logic block) that depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, we show that we are able to estimate detection probabilities of single-event faults/errors on IS-CAS'85 benchmarks with high accuracy (zero-error), linear space requirement complexity, and with an order of magnitude (≈5 times) reduction in estimation time over corresponding BDD based approaches.},
keywords={ belief networks, error detection, logic circuits, probabilistic logic Bayesian networks, IS-CAS'85 benchmark, LIFE-DAG, circuit logic, detection probability, error detection, error susceptibility, estimation time reduction, logic induced fault encoded directed acyclic graph, nanodomain logic block, probabilistic model, single event fault error model},
doi={10.1109/ICVD.2005.46},
ISSN={1063-9667 }, }

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks

S. Bhanja, K. Lingasubramanian and N. Ranganathan, "Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks,” 18^th International Conference in VLSI Design, pp.586-591, 2005.

@INPROCEEDINGS{1383338,
title={Estimation of switching activity in sequential circuits using dynamic Bayesian networks},
author={Bhanja, S. and Lingasubramanian, K. and Ranganathan, N.},
booktitle={VLSI Design, 2005. 18th International Conference on},
year={2005},
month={Jan.},
volume={},
number={},
pages={ 586-591},
abstract={ We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a dynamic Bayesian network. Dynamic Bayesian networks are extremely powerful in modeling high order temporal as well as spatial correlations; it is an exact model for the underlying conditional independencies. The attractive feature of this graphical representation of the joint probability function is that not only does it make the dependency relationships amongst the nodes explicit but it also serves as a computational mechanism for probabilistic inference. We report average errors in switching probability of 0.006, with errors tightly distributed around the mean error values, on IS-CAS'89 benchmark circuits involving up to 10000 signals.},
keywords={ belief networks, inference mechanisms, integrated circuit modelling, probability, sequential circuits, sequential switching, switching circuits IS-CAS'89, benchmark circuits, computational mechanism, dynamic Bayesian network, dynamic Bayesian networks, exact model, graphical representation, joint probability function, logic structure, nonsimulative probabilistic model, probabilistic inference, sequential circuits, spatiotemporal correlations, switching activity, switching probability, temporal dependency model},
doi={10.1109/ICVD.2005.93},
ISSN={1063-9667 }, }

Time and Space Efficient Method for Accurate Computation of Error Detection Probabilities

T. Rejimon and S. Bhanja, “Time and Space Efficient Method for Accurate Computation of Error Detection Probabilities”, IEE Proc. Computers & Digital Techniques, Volume 152, Issue 5, pp. 679 - 685 , 2005.


@ARTICLE{1532089,
title={Time and space efficient method for accurate computation of error detection probabilities in VLSI circuits},
author={Rejimon, T. and Bhanja, S.},
journal={Computers and Digital Techniques, IEE Proceedings -},
year={2005},
month={Sept.},
volume={152},
number={5},
pages={ 679-685},
abstract={The authors propose a novel fault/error model based on a graphical probabilistic framework. They arrive at the logic induced fault encoded directed acrylic graph (LIFE-DAG), which is proven to be a Bayesian network, capturing all spatial dependencies induced by the circuit logic. Bayesian networks are the minimal and exact representation of the joint probability distribution of the underlying probabilistic dependencies that not only use conditional independencies in modelling but also exploit them for achieving minimality and smart probabilistic inference. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in the nano-domain logic block) which depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, they show that they are able to estimate detection probabilities of faults/errors on ISCAS'85 benchmarks with high accuracy, linear space requirement complexity, and with an order of magnitude (≈5 times) reduction in estimation time over corresponding binary decision diagram based approaches.},
keywords={ VLSI, computational complexity, directed graphs, error detection, inference mechanisms, integrated circuit modelling, logic design, statistical distributions BDD based approach, Bayesian network, LIFE-DAG, VLSI circuits, accurate computation, circuit logic, error detection probabilities, error model, estimation time reduction, exact representation, fault model, graphical probabilistic framework, linear space requirement complexity, logic induced fault encoded directed acrylic graph, minimal representation, probabilistic inference, probability distribution, soft error susceptibility, space efficient method, time efficient method},
doi={10.1049/ip-cdt:20045106},
ISSN={1350-2387}, }