QCA Circuits for Robust Coplanar Crossing

S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi, “QCA Circuits for Robust Coplanar Crossing”, Accepted in, Journal of Electronic Testing: Theory and Applications (JETTA), Volume 23, Issue 2, pp. 193-210, 2007.

@article{bhanja2007qca,
title={{QCA circuits for robust coplanar crossing}},
author={Bhanja, S. and Ottavi, M. and Lombardi, F. and Pontarelli, S.},
journal={Journal of Electronic Testing},
volume={23},
number={2},
pages={193--210},
year={2007},
publisher={Springer}
}

Hierarchical Probabilistic Macromodeling for QCA Circuits

S. Srivastava and S. Bhanja, “Hierarchical Probabilistic Macromodeling for QCA Circuits”, in special issue of Nano Systems and Computing, IEEE Transactions on Computers, Volume56, Issue 2, pp. 174 – 190, 2007.

@ARTICLE{4042678,
title={Hierarchical Probabilistic Macromodeling for QCA Circuits},
author={Saket Srivastava and Sanjukta Bhanja},
journal={Computers, IEEE Transactions on},
year={2007},
month={Feb. },
volume={56},
number={2},
pages={174-190},
abstract={With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, we propose probabilistic macromodels for standard QCA circuit elements based on conditional probability characterization, defined over the output states given the input states. Any circuit model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate three uses for these macromodel-based circuits. First, the probabilistic macromodels allow us to model the logical function of QCA circuits at an abstract level - the "circuit" level - above the current practice of layout level in a time and space efficient manner. We show that the circuit level model is orders of magnitude faster and requires less space than layout level models, making the design and testing of large QCA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Second, the probabilistic macromodels abstract crucial device level characteristics such as polarization and low-energy error state configurations at the circuit level. We demonstrate how this macromodel-based circuit level representation can be used to infer the ground state probabilities, i.e., cell polarizations, a crucial QCA parameter. This allows us to study the thermal behavior of QCA circuits at a higher level of abstraction. Third, we demonstrate the use of these macromodels for error analysis. We show that low-energy state configurations of the macromodel circuit match those of the layout level, thus allowing us to isolate weak p- oints in circuits design at the circuit level itself},
keywords={cellular automata, integrated circuit modelling, probability, quantum computing, semiconductor quantum dotsBayesian network, QCA circuits, circuit thermal behavior, conditional probability characterization, error analysis, ground state probability inference, hierarchical probabilistic macromodeling, joint probability distribution, logic element macromodels, macromodel-based circuit level representation, quantum-dot cellular automata},
doi={10.1109/TC.2007.30},
ISSN={0018-9340}, }

Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps

S. Srivastava and S. Bhanja, "Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps", accepted for publication in IEEE/ACM Intl. Conf. on Microelectronic Systems Education (MSE), 2007.

WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course

S. Srivastava and S. Bhanja, “WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2007.