Journal Papers

1. Ollivier, S., Longofono, S., Dutta, P., Hu, J., Bhanja, S., & Jones, A. K. (2022). Toward comprehensive shifting fault tolerance for domain-wall memories with piett. IEEE Transactions on Computers, 72(4), 1095-1109.
   
2. Roxy, K., Longofono, S., Olliver, S., Bhanja, S., & Jones, A. K. (2022). Pinning fault mode modeling for DWM shifting. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(7), 3319-3323.
   
3. Hoque, A., Jones, A. K., & Bhanja, S. (2022). XDWM: A 2D Domain Wall Memory. IEEE Transactions on Nanotechnology, 21, 185-188.
   
4. Hoque, A., Rajaram, S., & Bhanja, S. (2021). A Study on Reconfigurable Nanomagnetic Array and Effect of Gilbert Damping on Reconfigurability. IEEE Transactions on Nanotechnology, 20, 503-506.
5. Roxy, K., Ollivier, S., Hoque, A., Longofono, S., Jones, A. K., & Bhanja, S. (2020).  A novel transverse read technique for domain-wall “racetrack” memories. IEEE Transactions on Nanotechnology, 19, 648-652.
6. Nance, J. A., Roxy, K. A., Bhanja, S., & Carman, G. P. (2020). Spin-Orbit Torque and Dipole Coupling for Nanomagnetic Array Programmability. IEEE Transactions on Magnetics.
7. Bautista, I., Sarkar, S., & Bhanja, S. (2020). MatlabHTM: A sequence memory model of neocortical layers for anomaly detection. SoftwareX, 11, 100491.
8. Roxy, K. A., & Bhanja, S. (2018). Reading Nanomagnetic Energy Minimizing Coprocessor. IEEE Transactions on Nanotechnology, 17(2), 368-372. 
9. Bhanja, S., Karunaratne, D. K., Panchumarthy, R., Rajaram, S., & Sarkar, S. (2016). Non-Boolean computing with nanomagnets for computer vision applications. Nature nanotechnology, 11(2), 177-183.
   
10.  Das, J., Scott, K., & Bhanja, S. (2016). MRAM PUF: Using geometric and resistive variations in MRAM cells. ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(1), 2. 
11. Das, J., Scott, K., Rajaram, S., Burgett, D., & Bhanja, S. (2015). MRAM PUF: A novel geometry based magnetic PUF with integrated CMOS. IEEE Transactions on Nanotechnology, 14(3), 436-443.
12.  Das, J., Alam, S. M., & Bhanja, S. (2014, September). Recent trends in spintronics-based nanomagnetic logic. In Spin (Vol. 4, No. 03, p. 1450004). World Scientific Publishing Company.
13.  Rajaram, S., Karunaratne, D. K., Sarkar, S., & Bhanja, S. (2013). Study of dipolar neighbor interaction on magnetization states of nano-magnetic disks. IEEE Transactions on Magnetics, 49(7), 3129-3132.
14.   Panchumarthy, R., Karunaratne, D. K., Sarkar, S., & Bhanja, S. (2013). Magnetic state estimator to characterize the magnetic states of nano-magnetic disks. IEEE Transactions on Magnetics, 49(7), 3545-3548.
15.  Das, J., Alam, S. M., & Bhanja, S. (2014). Nano magnetic STT-logic partitioning for optimum performance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(1), 90-98.
16.  Das, J., Alam, S. M., & Bhanja, S. (2012). Ultra-low power hybrid CMOS-magnetic logic architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(9), 2008-2016.
17.  Karunaratne, D. K., & Bhanja, S. (2012). Study of single layer and multilayer nano-magnetic logic architectures. Journal Of Applied Physics, 111(7), 07A928.
18.  Das, J., Alam, S. M., & Bhanja, S. (2011). Low power magnetic quantum cellular automata realization using magnetic multi-layer structures. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 1(3), 267-276.
19.  Lingasubramanian, K., Alam, S. M., & Bhanja, S. (2011). Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectronics Reliability, 51(2), 485-501.
20.   Kumari, A., Sarkar, S., Pulecio, J. F., Karunaratne, D. K., & Bhanja, S. (2011). Study of magnetization state transition in closely spaced nanomagnet two-dimensional array for computation. Journal of Applied Physics, 109(7), 07E513.
21.  Pulecio, J. F., Pendru, P. K., Kumari, A., & Bhanja, S. (2011). Magnetic cellular automata wire architectures. IEEE Transactions on Nanotechnology, 10(6), 1243-1248.
22.  Pulecio, J. F., & Bhanja, S. (2010). Magnetic cellular automata coplanar cross wire systems. Journal of applied physics, 107(3), 034308.
23.  Kumari, A., & Bhanja, S. (2011). Landauer clocking for magnetic cellular automata (mca) arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(4), 714-717.
24.  Srivastava, S., Asthana, A., Bhanja, S., & Sarkar, S. (2011, May). QCAPro-an error-power estimation tool for QCA circuit design. In Circuits and Systems (ISCAS), 2011 IEEE International Symposium on (pp. 2377-2380). IEEE.
25.  Rejimon, T., Lingasubramanian, K., & Bhanja, S. (2009). Probabilistic error modeling for nano-domain logic circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(1), 55-65.
26.  Bhanja, S., & Sarkar, S. (2008). Thermal switching error versus delay tradeoffs in clocked QCA circuits. IEEE transactions on very large scale integration (VLSI) systems, 16(5), 528-541.
27.  Srivastava, S., & Bhanja, S. (2008). Integrating a nanologic knowledge module into an undergraduate logic design course. IEEE Transactions on Education, 51(3), 349-355.
28.  Srivastava, S., & Bhanja, S. (2007). Hierarchical probabilistic macromodeling for QCA circuits. IEEE Transactions on Computers, 56(2), 174-190.
29. Bhanja, S., Ottavi, M., Lombardi, F., & Pontarelli, S. (2007). QCA circuits for robust coplanar crossing. Journal of Electronic Testing, 23(2-3), 193-210.
30.   Bhanja, S., & Sarkar, S. (2006). Probabilistic modeling of QCA circuits using Bayesian networks. IEEE Transactions on Nanotechnology, 5(6), 657-670.
31.  Rejimon, T., & Bhanja, S. (2006). A timing-aware probabilistic model for single-event-upset analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1130-1139.
32.  Bhanja, S., Lingasubramanian, K., & Ranganathan, N. (2006). A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Transactions on Design Automation of Electronic Systems (TODAES), 11(3), 773-796.
33.   Rejimon, T., & Bhanja, S. (2005). Time and space efficient method for accurate computation of error detection probabilities in VLSI circuits. IEE Proceedings-Computers and Digital Techniques, 152(5), 679-685.
34.  Bhanja, S., & Ranganathan, N. (2004). Cascaded bayesian inferencing for switching activity estimation with correlated inputs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(12), 1360-1370.
35.  Bhanja, S., & Ranganathan, N. (2003). Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(4), 558-567.

Toward comprehensive shifting fault tolerance for domain-wall memories with piett.

 Ollivier, S., Longofono, S., Dutta, P., Hu, J., Bhanja, S., & Jones, A. K. (2022). Toward comprehensive shifting fault tolerance for domain-wall memories with piett. IEEE Transactions on Computers, 72(4), 1095-1109.

Abstract:

Spintronic domain-wall memories (DWMs) offer improved memory density and energy compared to conventional memories, but are susceptible to shifting faults. We propose PIETT ( P inning, I nsertion, E rasure, and T ranslation-fault T olerance) for improved misalignment correction versus the state of the art. PIETT proposes a derived error correction combined with multi-domain access approach to detect and correct a minimum of three misalignment faults after an arbitrary shift distance. Moreover, the rate of both misalignment and pinning faults are characterized in DWM nanowires, demonstrating that pinning faults are a significant concern to DWM. As such, PIETT is the first method to combine correction of misalignment and pinning faults in random access DWMs. It also introduces novel PIETT Transverse Access Points (TAPs), which utilize a novel write access mode that can set/reset multiple domains in a single intrinsic operation and can store shift distance detection codes. By allowing checks between shifts of the intrinsic shift distance (e.g., 3 domains), using a single TAP per nanowire expands misalignment protection and determines the needed corrective shifts to correct faults in all nanowires. Two TAPs expands misalignment protection to correct misalignment by more than one position and detects pinning by detecting different shift distances at each extremity of the nanowire. PIETT leverages knowledge of pinned nanowire locations to guide a modified SECDED ECC with one additional parity bit stored in additional parity nanowires. Thus, PIETT in TAP mode can correct unlimited, potentially multi-position, misalignment faults and either up to three pinning faults or up to two pinning faults with up to one bit flip fault using scrubbing. PIETT provides 8 to 21 orders of magnitude improvement in mean-time-to-failure with similar or better area overhead and only a 1% system performance degradation compared to state of the art DWM misalignment correction.