A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC

V. K. Jain, S. Bhanja, G. H. Chapman, L. Doddannagari and N. Nguyen, “A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC”, Accepted for publication for IEEE SOC conference, pp. 243-246, 2005.

@INPROCEEDINGS{1554503,
title={A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC},
author={Jain, V.K. and Bhanja, S. and Chapman, G.H. and Doddannagari, L.},
booktitle={SOC Conference, 2005. Proceedings. IEEE International},
year={2005},
month={Sept.},
volume={},
number={},
pages={ 243-246},
abstract={A 3D heterogeneous system on a chip using a stack of planes has recently been proposed. While the sensors are located on the top plane, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on a reconfigurable computing array for its DSP plane. The advantages of such an approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. The authors presented the reconfigurable J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA_PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the benefits of reduced external interconnect, much reduced design time, and manageable testability. The paper discusses these cells, including a new concept, namely multi-granularity. The methodology for mapping algorithms is illustrated by two important examples, FIR filtering of signals and images and the independent component analysis (ICA) algorithm. Finally, the paper discusses the issue of defect tolerance, which is critical in attaining reasonable yields making chip manufacture feasible.},
keywords={ VLSI, digital signal processing chips, reconfigurable architectures, system-on-chip 3D heterogeneous system-on-chip, DSP plane, coarse grain VLSI cells, data fabric cell, defect tolerance, extended multiply accumulate cell, independent component analysis, reconfigurable J-platform, reconfigurable computing array, universal nonlinear cell},
doi={10.1109/SOCC.2005.1554503},
ISSN={}, }