A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor

V. Jain, S. Bhanja, G. Chapman, L. Doddannagari and N. Nguyen, “A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor”, Accepted for publication in IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.v77-v80, 2005.


@INPROCEEDINGS{1416244,
title={A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor},
author={Jain, V.K. and Bhanja, S. and Chapman, G.H. and Doddannagari, L. and Nguyen, N.},
booktitle={Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on},
year={2005},
month={March},
volume={5},
number={},
pages={ v/77-v/80 Vol. 5},
abstract={ A 3D heterogeneous sensor using a stacked chip has recently been proposed. While the sensors are located on one of the planes, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on its DSP plane, in particular on the implementation of the ICA (independent component analysis) algorithm in the DSP plane. ICA is a recently proposed method for solving the blind source separation problem. The objective is to recover the unobserved source signals from the observed mixtures without the knowledge of the mixing coefficients. We present a parallel architecture utilizing the reconfigurable J-platform, which employs coarse-gain VLSI cells. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the distinct advantages of reduced external interconnect, much reduced design time, and manageable testability. Additionally, the other algorithms needed for the 3D HSoC can also be mapped on to the same resources, by time multiplexing, thereby reducing the silicon area needed.},
keywords={ VLSI, blind source separation, digital signal processing chips, independent component analysis, parallel architectures, reconfigurable architectures, sensors, system-on-chip 3D HSoC, 3D heterogeneous sensor, ICA algorithm, blind source separation, coarse-gain VLSI cells, data-fabric cell, extended multiply accumulate cell, independent component analysis, parallel architecture, reconfigurable J-platform, sensor DSP plane, stacked chip sensor, time multiplexing, universal nonlinear cell},
doi={10.1109/ICASSP.2005.1416244},
ISSN={1520-6149}, }