Fast Estimation of Power Dissipation in QCA Circuits

S. Srivastava, S. Sarkar and S. Bhanja, “Estimation of Upper Bound of Power Dissipation in QCA Circuits”, Accepted, IEEE Transactions on Nanotechnology, vol. 8-1, pp. 116--127, 2009. @ARTICLE{4625949, title={Estimation of Upper Bound of Power Dissipation in QCA Circuits}, author={Srivastava, S. and Sarkar, S. and Bhanja, S.}, journal={Nanotechnology, IEEE Transactions on}, year={2009}, month={Jan. }, volume={8}, number={1}, pages={116-127}, abstract={Quantum-dot cellular automata (QCA) is a field-coupled computing paradigm. States of a cell change due to mutual interactions of either electrostatic or magnetic fields. Due to their small sizes, power is an important design parameter. In this paper, we derive an upper bound for power loss that will occur with input change, even with the circuit staying at respective ground states before and after the change. This bound is computationally efficient to compute for large QCA circuits since it just requires the knowledge of the before and after ground states due to input change. We categorize power loss in clocked QCA circuits into two types that are commonly used in circuit theory: switching power and leakage power. Leakage power loss is independent of input states and occurs when the clock energy is raised or lowered to depolarize or polarize a cell. Switching power is dependent on input combinations and occurs at the instant when the cell actually changes state. Total power loss is controlled by changing the rate of change of transitions in the clocking function. Our model provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in nonadiabatic operations and gives us the upper bound of power expended. We derive expressions for upper bounds of switching and leakage power that are easy to compute. Upper bounds obviously are pessimistic estimates, but are necessary to design robust circuits, leaving room for operational manufacturing variability. Given that thermal issues are critical to QCA designs, we show how our model can be valuable for QCA design automation in multiple ways. It can be used to quickly locate potential thermal hot spots in a QCA circuit. The model can also be used to correlate power loss with different input vector switching; power loss is dependent on the input vector. We can study the tradeoff between switching and leakage power in QCA circuits. And, we can use the model to vet different designs of the - - same logic, which we demonstrate for the full adder.}, keywords={cellular automata, ground states, integrated circuit design, quantum dotsQCA circuits, clock energy, ground states, leakage power, power dissipation, power loss, quantum-dot cellular automata, switching power, upper bound estimation}, doi={10.1109/TNANO.2008.2005408}, ISSN={1536-125X}, }

 

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Probabilistic Error Model for Nano-Domain Logic Circuits

T. Rejimon, K. Lingasubramanian and S. Bhanja, “Probabilistic Error Model for Nano-Domain Logic Circuits”, Accepted, IEEE Transactions on VLSI, 2008.

@ARTICLE{4703183,
title={Probabilistic Error Modeling for Nano-Domain Logic Circuits},
author={Rejimon, T. and Lingasubramanian, K. and Bhanja, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2009},
month={Jan. },
volume={17},
number={1},
pages={55-65},
abstract={In nano-domain logic circuits, errors generated are transient in nature and will arise due to the uncertainty or the unreliability of the computing element itself. This type of errors - which we refer to as dynamic errors - are to be distinguished from traditional faults and radiation related errors. Due to these highly likely dynamic errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic. We propose a probabilistic error model based on Bayesian networks to estimate this expected output error probability, given dynamic error probabilities in each device since this estimate is crucial for nano-domain circuit designers to be able to compare and rank designs based on the expected output error. We estimate the overall output error probability by comparing the outputs of a dynamic error-encoded model with an ideal logic model. We prove that this probabilistic framework is a compact and minimal representation of the overall effect of dynamic errors in a circuit. We use both exact and approximate Bayesian inference schemes for propagation of probabilities. The exact inference shows better time performance than the state-of-the art by exploiting conditional independencies exhibited in the underlying probabilistic framework. However, exact inference is worst case NP-hard and can handle only small circuits. Hence, we use two approximate inference schemes for medium size benchmarks. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results. We have performed our experiments on ISCAS'85 and MCNC benchmark circuits. We explore our probabilistic model to calculate: 1) error sensitivity of individual gates in a circuit; 2) compute overall exact error probabilities for small circuits; 3) compute approximate error probabilities for medium sized benchmarks using two stochastic sampling schemes; 4) compare and vet design with respect to dynamic errors; 5) characterize the input space for desired output characteristics by utilizing the unique backtracking capability of Bayesian networks (inverse problem); and 6) to apply selective redundancy to highly sensitive nodes for error tolerant designs.},
keywords={belief networks, error statistics, inference mechanisms, logic CAD, logic circuits, logic gates, network synthesisBayesian inference schemes, Bayesian networks, dynamic error-encoded model, error sensitivity, error tolerant designs, logic gates, nano-domain computing, nano-domain logic circuits, output error probability, probabilistic error modeling, radiation related errors, stochastic sampling schemes},
doi={10.1109/TVLSI.2008.2003167},
ISSN={1063-8210}, }

Dr. Bhanja receives promotion to Associate Professor

Dr. Bhanja gets promoted to Associated Professor with Tenure.