Tuesday, January 6, 2015

Team "Secret" comprising of Jayita Das and Kevin Scott is the first-place winner of NYU organized Cybersecurity event "The Embedded Security Challenge"

The Embedded Security Challenge deals with the security and trustworthiness of hardware. This year, students were challenged to focus on emerging technologies and materials and to prove to us why they are valuable and secure. Representatives of 10 student teams were invited to the finals, where they presented their research to judges. All three winners were from Florida:

1st place: SECurity Researchers in Emerging Technology (SECRET), University of South Florida—Jayita Das and Kevin P. Scott


USF teams receive grants to develop socially beneficial products

Sanjukta Bhanja's I-Corps Project was featured in http://www.83degreesmedia.com

Read more--

http://www.83degreesmedia.com/innovationnews/NSF120214.aspx

Jayita Das Receives Grace Hopper Celebration in Computing Travel Award

http://www.eng.usf.edu/about/news/07-16-14%20Jayita%20Das%20Receives%20Grace%20Hopper%20Award.pdf

Javier Pulecio’s Research Featured on the Cover of Applied Physics Letters

http://www.eng.usf.edu/pdf/09-30-14%20Javier%20Pulecio.pdf
\A recently published paper, Symmetry breaking of magnetic vortices before annihilation, by Javier Pulecio, et. al., PhD ’10, appeared on the cover of the September 29, 2014 issue of Applied Physics Letters, Volume 105, Issue 13. 

Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives

Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives (Lecture Notes in Computer Science / Theoretical Computer Science and General Issues) Paperback – June 30, 2014

MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS

"MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS", Jayita Das, Kevin Scott, Srinath Rajaram, Drew Burgett, Sanjukta Bhanja, Accepted in IEEE Transactions on Nanotechnology, 2015.

Abstract—This manuscript addresses a novel MRAM-based Physically Unclonable Function (PUF). The PUF responses are generated using the unique energy-tilt, which is an outcome of the random geometric variations in the MRAM cells. We have verified relevant attributes of this PUF through extensive magnetic simulations and in-house fabrication results. Our fabricated PUF cells generate entropy as high as 0.99, which is comparable to most of its competitors. To our knowledge, the footprint of the PUF cells is also lower than the majority of silicon PUFs. Also, the authentication control algorithm for this PUF requires very low additional control-steps. We conclude our discussion of this novel PUF with a study of authentication overhead and protocols required by the PUF system in terms of area, power and delay.

RECENT TRENDS IN SPINTRONICS-BASED NANOMAGNETIC LOGIC

JAYITA DAS, SYED M. ALAM, and SANJUKTA BHANJA, SPIN 04, 1450004 (2014) [23 pages] DOI: 10.1142/S2010324714500040      

Abstract: With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy (Ni80Fe14Mo5X1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.