Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps

S. Srivastava and S. Bhanja, "Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps", accepted for publication in IEEE/ACM Intl. Conf. on Microelectronic Systems Education (MSE), 2007.

WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course

S. Srivastava and S. Bhanja, “WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2007.

Dr. Alam (Freescale Semiconductors) delivers Invited Colloquium

Dr. Syed Alam delivers Invited Colloquium talk on 3-Dimensional Integrated Cirsuit, Summer 2007.

Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits

S. Srivastava, S. Sarkar and S. Bhanja, “Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits”, Accepted for publication in IEEE conference on nanotechnology, Cincinnati, 2006. @INPROCEEDINGS{1717105, title={Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits}, author={ Srivastava, S. and Sarkar, S. and Bhanja, S.}, booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on}, year={2006}, month={June}, volume={1}, number={}, pages={ 375-378}, abstract={ The goal of this work is to present a worst-case power estimation model for QCA designs. Based on existing power models, we derive upper bound for power dissipation that occurs for non-adiabatic clock switching and represents the worst-case power estimate. This upper bound is easy to compute and does not require simulation of quantum dynamics. Given the criticality of thermal issues and the inherent process variabilities at nano-scale, such worst case estimates, that is easy to compute, will be useful at higher levels of design abstractions, so as to vet different designs or to create power macromodels for different circuit components. There are three power dissipation events for each cell: first when the clock goes up, second when the input switches, and third when the clock goes down. The first and the third events are analogous to “leakage” power in CMOS designs in that there is dissipation even when there is no change in inputs. The second event can be related to “switching” power in CMOS and is dependent on inputs. The proportion between these two types of dissipations is strongly dependent on the clock energy. In addition to the clock, the other determining factors are cell polarization, kink energy, and quantum relaxation time. We demonstrate the model using majority gate and inverter, which are critical circuit components.}, doi={}, ISSN={}, }

 

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Switching Error Modes of QCA Circuits

S. Bhanja and S. Sarkar, “Switching Error Modes of QCA Circuits”, Accepted for publication in IEEE conference on nanotechnology, Cincinnati, 2006.

@INPROCEEDINGS{1717107,
title={Switching Error Modes of QCA Circuits},
author={ Bhanja, S. and Sarkar, S.},
booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on},
year={2006},
month={June},
volume={1},
number={},
pages={ 383-386},
abstract={ The Quantum-dot Cellular Automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a collection of QCA cells, with two possible ground states for each cell. A four phased clocking is used to keep the computations at the ground state throughout the circuit. Computing errors in QCA circuits can arise due to the failure of the clocking scheme to switch portions of the circuit to its new ground state with change in input. To study these switching errors we need to consider low-energy state configurations of QCA circuits. However, current QCA simulators compute just the ground state configuration of a QCA arrangement. In this paper, we offer an efficient method, based on graphical probabilistic models, to compute the N-lowest energy modes of a clocked QCA circuit. The overall low-energy, excited, spectrum of multiple clocking zones is constructed by concatenating the excited spectra of the individual clocking zones. We demonstrate the use of this error model by comparing different designs of wire crossings.},
doi={},
ISSN={}, }

Bayesian Macromodeling for Circuit Level QCA Design

S. Srivastava and S. Bhanja, “Bayesian Macromodeling for Circuit Level QCA Design”, Accepted for publication in IEEE conference on nanotechnology, Cincinnati, 2006.

@INPROCEEDINGS{1717009,
title={Bayesian Macromodeling for Circuit Level QCA Design},
author={ Srivastava, S. and Bhanja, S.},
booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on},
year={2006},
month={June},
volume={1},
number={},
pages={ 31-34},
abstract={ We present a probabilistic methodology to model and abstract the behavior of quantum-dot cellular automata circuit(QCA) at “ circuit level” above the current practice of layout level. These macromodels provide input-output relationship of components (a set of QCA cells emulating a logical function) that are faithful to the underlying quantum effects. We show the macromodeling of a few key circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners. In this work, we demostrate how we can make use of these macromodels to abstract the logical function of QCA circuits and to extract crucial device level characteristics such as polarization and low-energy error state configurations by circuit level Bayesian model, accurately accounting for temperature and other device level parameters. We also demonstrate how this macromodel based design can be used effectively in analysing and isolating the weak spots in the design at circuit level itself.},
doi={},
ISSN={}, }

Probabilistic Error Model for Unreliable Nano-Logic gates

T. Rejimon and S. Bhanja, “Probabilistic Error Model for Unreliable Nano-Logic gates”, Accepted for publication in IEEE conference on nanotechnology, pp. Cincinnati, 2006.

@INPROCEEDINGS{1717013,
title={Probabilistic Error Model for Unreliable Nano-logic Gates},
author={ Rejimon, T. and Bhanja, S.},
booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on},
year={2006},
month={June},
volume={1},
number={},
pages={ 47-50},
abstract={ We propose a novel formalism, based on probabilistic Bayesian networks, to capture, analyze, and model dynamic errors at nano logic for probabilistic reliability analysis. It will be important for circuit designers to be able to compare and rank designs based on the expected output error, which is a measure of reliability. We propose an error model to estimate this expected output error probability, given the probability of these errors in each device. We estimate the overall output error probability by comparing the outputs of an ideal logic model with a dynamic error-encoded model. We use of Bayesian inference schemes for propagation of probabilities. Since exact inference is worst case NP-hard, we use two approximate inference schemes based on importance sampling, namely EPIS(Evidence Prepropagated Importance Sampling) and PLS (Probabilistic Logic Sampling), for handling mid-size benchmarks having up to 3500 gates. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results.},
doi={},
ISSN={}, }