Technical Program Co-chair

Dr. Bhanja was selected as Technical Program Co-Chair ACM Great Lakes Symposium on VLSI, 2008

Outstanding Faculty Researcher award

Dr. Bhanja receives University of South Florida “Outstanding Faculty Research Achievement Award”, 2008.

PASI

Javier Pulecio receives Pan American Science Institute scholarship

DSRC Invited Speaker

Dr. Bhanja delivers Invited talk sponsored by DSRC workshop held at Stanford University.

Sloan Fellowship

Javier Pulecio receives Alfred P Sloan fellowship

Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits

A. Shareef, K. Lingasubramanian and S. Bhanja, “Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits”, Accepted for publication in IEEE conference on nanotechnology, Arlington, 2008.

@INPROCEEDINGS{4617250,
title={Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits},
author={Shareef, A. and Lingasubramanian, K. and Bhanja, S.},
booktitle={Nanotechnology, 2008. NANO '08. 8th IEEE Conference on},
year={2008},
month={Aug.},
volume={},
number={},
pages={895-898},
abstract={Devices in nano-regime have inherent propensity for errors due to their very stochastic nature there by making Reliability modeling and evaluation as one of the major issues. To account for these issues, probabilistic models would be more appropriate than deterministic models as they can represent the transient nature of the nano-devices perfectly. In this work, we have used a probabilistic model to study the erroneous behavior of digital logic circuits. Inference on this probabilistic model is performed using junction tree algorithm. Using the unique feature of the junction tree, namely backtracking or Two phase propagation of evidence, we were able to rank or select a subset of input instantiations which are more likely to aggregate error at the output for any given circuit. Using these results we have performed a temporal redundancy scheme using triple temporal redundancy (TTR). As safety- centric designs need worst case behavior study, we have focused on both worst case and average behavior. We have also performed a spatial redundancy scheme using cascaded triple modular redundancy (CTMR) [9], and evaluated the results with those of the temporal redundancy scheme with respect to standard ISCAS'85 benchmark circuits and suggested the best error mitigation scheme for both average and maximum case. Experimental results show that spatial redundancy scheme, irrespective of technique used, is effective in mitigating average output error. Where as Temporal redundancy scheme has out- weighted spatial redundancy scheme in mitigating maximum error.},
keywords={backtracking, benchmark testing, fault trees, nanoelectronics, redundancyISCAS'85 benchmark circuits, backtracking, cascaded triple modular redundancy, digital logic circuits, error mitigation scheme, junction tree algorithm, nanoelectronic circuits, probabilistic model, reliability enhancement, reliability modeling, safety-centric designs, spatial redundancy scheme, temporal redundancy scheme, triple temporal redundancy, two phase propagation of evidence},
doi={10.1109/NANO.2008.268},
ISSN={}, }

Error-Power Tradeoffs in QCA Design

S. Srivastava, S. Sarkar and S. Bhanja, “Error-Power Tradeoffs in QCA Design”, Accepted for publication in IEEE conference on nanotechnology, Arlington, 2008. @INPROCEEDINGS{4617140, title={Error-Power Tradeoffs in QCA Design}, author={Srivastava, S. and Sarkar, S. and Bhanja, S.}, booktitle={Nanotechnology, 2008. NANO '08. 8th IEEE Conference on}, year={2008}, month={Aug.}, volume={}, number={}, pages={530-533}, abstract={In this work we present an error-power tradeoff study in a Quantum-dot Cellular Automata (QCA) circuit design. Device parameter variation to optimize performance is a very crucial step in the development of a technology. In this work we vary the maximum kink energy of a QCA circuit to perform an error-power tradeoff study in QCA design. We make use of graphical probabilistic models to estimate polarization errors and non-adiabatic energy dissipated in a clocked QCA circuit and demonstrate the tradeoff studies on the basic QCA circuits such as majority gate and inverter. We also show how this study can be used by comparing two single bit adder designs. The study will be of great use to designers and fabrication scientists to choose the most optimum size and spacing of QCA cells to fabricate QCA logic designs.}, keywords={cellular automata, logic design, quantum computing, quantum dots, quantum well devicesQCA circuit design, QCA logic design, clocked QCA circuit, error-power tradeoffs, graphical probabilistic model, maximum kink energy, nonadiabatic energy dissipation, polarization errors, quantum-dot cellular automata}, doi={10.1109/NANO.2008.158}, ISSN={}, }

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