Probabilistic Error Model for Nano-Domain Logic Circuits

T. Rejimon, K. Lingasubramanian and S. Bhanja, “Probabilistic Error Model for Nano-Domain Logic Circuits”, Accepted, IEEE Transactions on VLSI, 2008.

@ARTICLE{4703183,
title={Probabilistic Error Modeling for Nano-Domain Logic Circuits},
author={Rejimon, T. and Lingasubramanian, K. and Bhanja, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2009},
month={Jan. },
volume={17},
number={1},
pages={55-65},
abstract={In nano-domain logic circuits, errors generated are transient in nature and will arise due to the uncertainty or the unreliability of the computing element itself. This type of errors - which we refer to as dynamic errors - are to be distinguished from traditional faults and radiation related errors. Due to these highly likely dynamic errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic. We propose a probabilistic error model based on Bayesian networks to estimate this expected output error probability, given dynamic error probabilities in each device since this estimate is crucial for nano-domain circuit designers to be able to compare and rank designs based on the expected output error. We estimate the overall output error probability by comparing the outputs of a dynamic error-encoded model with an ideal logic model. We prove that this probabilistic framework is a compact and minimal representation of the overall effect of dynamic errors in a circuit. We use both exact and approximate Bayesian inference schemes for propagation of probabilities. The exact inference shows better time performance than the state-of-the art by exploiting conditional independencies exhibited in the underlying probabilistic framework. However, exact inference is worst case NP-hard and can handle only small circuits. Hence, we use two approximate inference schemes for medium size benchmarks. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results. We have performed our experiments on ISCAS'85 and MCNC benchmark circuits. We explore our probabilistic model to calculate: 1) error sensitivity of individual gates in a circuit; 2) compute overall exact error probabilities for small circuits; 3) compute approximate error probabilities for medium sized benchmarks using two stochastic sampling schemes; 4) compare and vet design with respect to dynamic errors; 5) characterize the input space for desired output characteristics by utilizing the unique backtracking capability of Bayesian networks (inverse problem); and 6) to apply selective redundancy to highly sensitive nodes for error tolerant designs.},
keywords={belief networks, error statistics, inference mechanisms, logic CAD, logic circuits, logic gates, network synthesisBayesian inference schemes, Bayesian networks, dynamic error-encoded model, error sensitivity, error tolerant designs, logic gates, nano-domain computing, nano-domain logic circuits, output error probability, probabilistic error modeling, radiation related errors, stochastic sampling schemes},
doi={10.1109/TVLSI.2008.2003167},
ISSN={1063-8210}, }

Dr. Bhanja receives promotion to Associate Professor

Dr. Bhanja gets promoted to Associated Professor with Tenure.

CNT logic knowledge module integrated in digital CMOS logic design

A. Kumari and S. Bhanja, "CNT logic knowledge module integrated in digital CMOS logic design", IEEE Microelectronics Semiconductor Education, 2009

Magnetic Cellular Automata (MCA) arrays under spatially varying field

Magnetic Cellular Automata (MCA) arrays under spatially varying field Kumari, A. Bhanja, S. Electr. Eng. Dept., Univ. of South Florida, Tampa, FL, USA This paper appears in: Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE Publication Date: 2-5 June 2009 On page(s): 50 - 53 Location: Traverse City, MI ISBN: 978-1-4244-4695-7 Digital Object Identifier: 10.1109/NMDC.2009.5167567 Current Version Published: 2009-07-21

Abstract Magnetic Cellular Automata (MCA) is a variant of Quantum-dot-cellular automata (QCA) where neighboring single-domain nano-magnets (also termed as magnetic cell) process and propagate information (logic 1 or logic 0) through mutual interaction. The attractive nature of this framework is that not only room temperature operations are feasible but also interaction between neighbors is central to information processing as opposed to creating interference. In this work, we explore spatially moving Landauer clocking scheme for MCA arrays (length of eight, sixteen and thirty-two cells) and show the role and effectiveness of the clock in propagating logic signal from input to output without magnetic frustration. Simulation performed in OOMMF.

Magnetic Cellular Automata wires

Magnetic Cellular Automata wires

Pulecio, J.F. Bhanja, S.
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
This paper appears in: Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE
Publication Date: 2-5 June 2009
On page(s): 73 - 75
Location: Traverse City, MI
ISBN: 978-1-4244-4695-7
Digital Object Identifier: 10.1109/NMDC.2009.5167576
Current Version Published: 2009-07-21
Abstract
Magnetic Cellular Automata (MCA) is a novel take on an alternative technological actualization of Boolean logic machines. Not only has it been able to prototypically demonstrate successful operation of logical gates at room temperature; all key components necessary to implement any Boolean function has been realized. We present work further reducing the size of the single domain nano-magnet, approximately 100 times 50 times 30 nm, and physically implement two types of MCA wire architectures ferromagnetic and anti-ferromagnetic. We report the first physical implementation of shape engineered ferromagnetic wires and compare both wires under saturating magnetic fields in the Z direction. We have concluded experimentally, that for conventional data propagation between logical networks, ferromagnetic wires provide extremely stable operation. The high order of coupling we found under saturating magnetic fields demonstrates the flexible clocking nature of ferromagnetic wires and inches the technology closer to implementing complex circuitry.

Invited Paper in IEEE NMDC, 2009

Anita Kumari's work published in IEEE NMDC gets accepted as Invited Paper, 2009

Dr. Bhanja is selected as Program Co-Chair, IEEE ISVLSI, 2009

Dr. Bhanja was selected as Technical Program Co-chair for IEEE ISVLSI, 2009