http://www.eng.usf.edu/about/news/07-16-14%20Jayita%20Das%20Receives%20Grace%20Hopper%20Award.pdf
Tuesday, January 6, 2015
Javier Pulecio’s Research Featured on the Cover of Applied Physics Letters
http://www.eng.usf.edu/pdf/09-30-14%20Javier%20Pulecio.pdf
\A recently published paper, Symmetry breaking of magnetic vortices before annihilation, by Javier Pulecio, et. al., PhD ’10, appeared on the cover of the September 29, 2014 issue of Applied Physics Letters, Volume 105, Issue 13.
\A recently published paper, Symmetry breaking of magnetic vortices before annihilation, by Javier Pulecio, et. al., PhD ’10, appeared on the cover of the September 29, 2014 issue of Applied Physics Letters, Volume 105, Issue 13.
Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives
Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives (Lecture Notes in Computer Science / Theoretical Computer Science and General Issues) Paperback – June 30, 2014
Field-coupled nanocomputing (FCN) paradigms offer fundamentally new approaches to digital information processing that do not utilize transistors or require charge transport. Information transfer and computation are achieved in FCN via local field interactions between nanoscale building blocks that are organized in patterned arrays. Several FCN paradigms are currently under active investigation, including quantum-dot cellular automata (QCA), molecular quantum cellular automata (MQCA), nanomagnetic logic (NML), and atomic quantum cellular automata (AQCA). Each of these paradigms has a number of unique features that make it attractive as a candidate for post-CMOS nanocomputing, and each faces critical challenges to realization.This State-of-the-Art-Survey provides a snapshot of the current developments and novel research directions in the area of FCN. The book is divided into five sections. The first part, Field-Coupled Nanocomputing Paradigms, provides valuable background information and perspectives on the QDCA, MQCA, NML, and AQCA paradigms and their evolution. The second section, Circuits and Architectures, addresses a wide variety of current research on FCN clocking strategies, logic synthesis, circuit design and test, logic-in-memory, hardware security, and architecture. The third section, Modeling and Simulation, considers the theoretical modeling and computer simulation of large FCN circuits, as well as the use of simulations for gleaning physical insight into elementary FCN building blocks. The fourth section, Irreversibility and Dissipation, considers the dissipative consequences of irreversible information loss in FCN circuits, their quantification, and their connection to circuit structure. The fifth section, The Road Ahead: Opportunities and Challenges, includes an edited transcript of the panel discussion that concluded the 2013 Workshop on Field-Coupled Nanocomputing.
MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS
"MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS", Jayita Das, Kevin Scott, Srinath Rajaram, Drew Burgett, Sanjukta Bhanja, Accepted in IEEE Transactions on Nanotechnology, 2015.
RECENT TRENDS IN SPINTRONICS-BASED NANOMAGNETIC LOGIC
JAYITA DAS, SYED M. ALAM, and SANJUKTA BHANJA,
SPIN
04, 1450004 (2014) [23 pages]
DOI: 10.1142/S2010324714500040
Abstract: With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy (Ni80Fe14Mo5X1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.
Abstract: With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy (Ni80Fe14Mo5X1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.
Friday, December 27, 2013
Drew Burgett Selected as 2013 NASA Space Technology Research Fellow
http://www.eng.usf.edu/about/news/6-11-13%20Burgett%20Selected%20for%20NASA%20Fellowship.pdf
Tuesday, August 13, 2013
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