Direct Quadratic Minimization Using Magnetic Field-Based Computing Sarkar, S. Bhanja, S. |
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| Abstract We explore an unconventional front in computing,which we call magnetic field-based computing (MFC), that harnesses the energy minimization aspects of a collection of nanomagnets to solve directly quadratic energy minimization problems, such as those arising in computationaolly intensive computer vision tasks. The Hamiltonian of a collection of bipolar nanomagnets is governed by the pairwise dipolar interactions.The ground state of a nanomagnet collection minimizes this Hamiltonian. We have devised a computational method, based on multi-dimensional scaling, to decide upon the spatial arrangement of nanomagnets that matches a particular quadratic minimization problem. Each variable is represented by a nanomagnet and the distances between them are such that the dipolar interactions match the corresponding pairwise energy term in the original optimization problem. We select the nanomagnets that participate in a specific computation from a field of regularly placed nanomagnets. The nanomagnets that do not participate are deselected using transverse magnetic fields. We demonstrate these ideas by solving Landau-Lifshitz equations as implemented in the NISTpsilas micro-magnetic OOMMF software. |
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Tuesday, September 16, 2008
Direct Quadratic Minimization Using Magnetic Field-Based Computing
Technical Program Co-chair
Dr. Bhanja was selected as Technical Program Co-Chair ACM Great Lakes Symposium on VLSI, 2008
Outstanding Faculty Researcher award
Dr. Bhanja receives University of South Florida “Outstanding Faculty Research Achievement Award”, 2008.
DSRC Invited Speaker
Dr. Bhanja delivers Invited talk sponsored by DSRC workshop held at Stanford University.
Wednesday, September 10, 2008
Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits
A. Shareef, K. Lingasubramanian and S. Bhanja, “Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits”, Accepted for publication in IEEE conference on nanotechnology, Arlington, 2008.
@INPROCEEDINGS{4617250,
title={Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits},
author={Shareef, A. and Lingasubramanian, K. and Bhanja, S.},
booktitle={Nanotechnology, 2008. NANO '08. 8th IEEE Conference on},
year={2008},
month={Aug.},
volume={},
number={},
pages={895-898},
abstract={Devices in nano-regime have inherent propensity for errors due to their very stochastic nature there by making Reliability modeling and evaluation as one of the major issues. To account for these issues, probabilistic models would be more appropriate than deterministic models as they can represent the transient nature of the nano-devices perfectly. In this work, we have used a probabilistic model to study the erroneous behavior of digital logic circuits. Inference on this probabilistic model is performed using junction tree algorithm. Using the unique feature of the junction tree, namely backtracking or Two phase propagation of evidence, we were able to rank or select a subset of input instantiations which are more likely to aggregate error at the output for any given circuit. Using these results we have performed a temporal redundancy scheme using triple temporal redundancy (TTR). As safety- centric designs need worst case behavior study, we have focused on both worst case and average behavior. We have also performed a spatial redundancy scheme using cascaded triple modular redundancy (CTMR) [9], and evaluated the results with those of the temporal redundancy scheme with respect to standard ISCAS'85 benchmark circuits and suggested the best error mitigation scheme for both average and maximum case. Experimental results show that spatial redundancy scheme, irrespective of technique used, is effective in mitigating average output error. Where as Temporal redundancy scheme has out- weighted spatial redundancy scheme in mitigating maximum error.},
keywords={backtracking, benchmark testing, fault trees, nanoelectronics, redundancyISCAS'85 benchmark circuits, backtracking, cascaded triple modular redundancy, digital logic circuits, error mitigation scheme, junction tree algorithm, nanoelectronic circuits, probabilistic model, reliability enhancement, reliability modeling, safety-centric designs, spatial redundancy scheme, temporal redundancy scheme, triple temporal redundancy, two phase propagation of evidence},
doi={10.1109/NANO.2008.268},
ISSN={}, }
@INPROCEEDINGS{4617250,
title={Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits},
author={Shareef, A. and Lingasubramanian, K. and Bhanja, S.},
booktitle={Nanotechnology, 2008. NANO '08. 8th IEEE Conference on},
year={2008},
month={Aug.},
volume={},
number={},
pages={895-898},
abstract={Devices in nano-regime have inherent propensity for errors due to their very stochastic nature there by making Reliability modeling and evaluation as one of the major issues. To account for these issues, probabilistic models would be more appropriate than deterministic models as they can represent the transient nature of the nano-devices perfectly. In this work, we have used a probabilistic model to study the erroneous behavior of digital logic circuits. Inference on this probabilistic model is performed using junction tree algorithm. Using the unique feature of the junction tree, namely backtracking or Two phase propagation of evidence, we were able to rank or select a subset of input instantiations which are more likely to aggregate error at the output for any given circuit. Using these results we have performed a temporal redundancy scheme using triple temporal redundancy (TTR). As safety- centric designs need worst case behavior study, we have focused on both worst case and average behavior. We have also performed a spatial redundancy scheme using cascaded triple modular redundancy (CTMR) [9], and evaluated the results with those of the temporal redundancy scheme with respect to standard ISCAS'85 benchmark circuits and suggested the best error mitigation scheme for both average and maximum case. Experimental results show that spatial redundancy scheme, irrespective of technique used, is effective in mitigating average output error. Where as Temporal redundancy scheme has out- weighted spatial redundancy scheme in mitigating maximum error.},
keywords={backtracking, benchmark testing, fault trees, nanoelectronics, redundancyISCAS'85 benchmark circuits, backtracking, cascaded triple modular redundancy, digital logic circuits, error mitigation scheme, junction tree algorithm, nanoelectronic circuits, probabilistic model, reliability enhancement, reliability modeling, safety-centric designs, spatial redundancy scheme, temporal redundancy scheme, triple temporal redundancy, two phase propagation of evidence},
doi={10.1109/NANO.2008.268},
ISSN={}, }
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