Probabilistic Modeling of QCA Circuits using Bayesian Networks

S. Bhanja and S. Sarkar, “Probabilistic Modeling of QCA Circuits using Bayesian Networks”, Accepted for publication in IEEE transaction on Nanotechnology, Volume 5, Issue 6, pp. 657 – 670, 2006.

@ARTICLE{4011919,
title={Probabilistic Modeling of QCA Circuits Using Bayesian Networks},
author={Bhanja, S. and Sarkar, S.},
journal={Nanotechnology, IEEE Transactions on},
year={2006},
month={Nov. },
volume={5},
number={6},
pages={657-670},
abstract={To push the frontiers of quantum-dot cellar automata (QCA) based circuit design, it is necessary to have design and analysis tools at multiple levels of abstractions. To characterize the performance of QCA circuits it is not sufficient to specify just the binary discrete states (0 or 1) of the individual cells, but also the probabilities of observing these states. We present an efficient method based on graphical probabilistic models, called Bayesian networks (BNs), to model these steady-state cell state probabilities, given input states. The nodes of the BN are random variables, representing individual cells, and the links between them capture the dependencies among them. BNs are minimal, factored, representation of the overall joint probability of the cell states. The method is fast and its complexity is shown to be linear in terms of the number of cells. This BN model allows us to analyze clocked QCA circuits in terms of quantum- mechanical quantities, such as steady-state polarization and thermal ratios for each cell, without the need for full quantum-mechanical simulation, which is known to be very slow and is best postponed to the final stages of the design process. We can also estimate the most likely (or ground) state configuration for all the cells and the lowest energy configuration that results in output errors. We validate the model with steady-state probabilities computed by the Hartree-Fock self-consistent approximation (HT-SCA). Using full adder designs, we demonstrate the ability to compare and contrast QCA circuit designs with respect to the variation of the output state probabilities with temperature and input. We also show how weak spots in clocked QCA circuit designs can be found using our model by comparing the (most likely) ground-state configuration with the next most likely energy state configuration that results in output error},
keywords={Bayes methods, HF calculations, SCF calculations, cellular automata, logic circuits, logic design, nanotechnology, network synthesis, probability, semiconductor quantum dotsBayesian networks, Hartree-Fock self-consistent approximation, Markov models, QCA circuits, binary discrete states, circuit design, energy state configuration, full adder designs, ground-state configuration, nanocomputing, nanotechnology, probabilistic modeling, quantum-dot cellular automata, quantum-mechanical simulation, steady-state cell state probability, steady-state polarization, stochastic logic circuits},
doi={10.1109/TNANO.2006.883474},
ISSN={1536-125X}, }

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

T. Rejimon and S. Bhanja, “A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis”, Accepted for publication in IEEE Transactions on VLSI Systems, Volume 14, Issue 10, pp.1130-1139, 2006. (A preliminary version of this paper was nominated for “Best Paper Award” and received “Honorable Mention award” in Intl. Conference of VLSI Design 2006).

@ARTICLE{1715349,
title={A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis},
author={Rejimon, T. and Bhanja, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2006},
month={Oct. },
volume={14},
number={10},
pages={1130-1139},
abstract={With device size shrinking and fast rising frequency ranges, the effect of cosmic radiations and alpha particles known as single-event upset (SEU) and single-event transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of SEU sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure, and gate delays on SEU sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but it also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate nonsimulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time},
keywords={belief networks, integrated circuit modelling, integrated circuit reliability, integrated logic circuits, radiation effectsBayesian inference, Bayesian network, SEU sensitivity, alpha particles effect, circuit structure, cosmic radiations effect, device size, gate delays, logic circuits, logic level design abstraction, radiation tolerant designs, single joint probability distribution function, single-event transients, single-event upset, soft error hardening techniques, timing-aware probabilistic model},
doi={10.1109/TVLSI.2006.884165},
ISSN={1063-8210}, }

A Stimulus-free Graphical Probabilistic Switching Model for Sequential Circuits using Dynamic Bayesian Networks

S. Bhanja, K. Lingasubramanian and N. Ranganathan, “A Stimulus-free Graphical Probabilistic Switching Model for Sequential Circuits using Dynamic Bayesian Networks” Accepted for publication in ACM Transactions on Design Automation and Electronic System, Volume 11, Issue 3, pp. 773-796, 2006.

@article{bhanja2006stimulus,
title={{A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks}},
author={Bhanja, S. and Lingasubramanian, K. and Ranganathan, N.},
journal={ACM Transactions on Design Automation of Electronic Systems (TODAES)},
volume={11},
number={3},
pages={773--796},
year={2006},
publisher={ACM New York, NY, USA}
}

WIP- Dominant Sensory Mode based Groups in VLSI Classes

S. Bhanja, “WIP- Dominant Sensory Mode based Groups in VLSI Classes”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2006.

@conference{bhanja2006work,
title={{Work in Progress: Dominant Sensory Mode based Groups in VLSI Classes}},
author={Bhanja, S.},
booktitle={Frontiers in Education Conference, 36th Annual},
pages={14--15},
year={2006}
}

Abstract:


This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class. Our motivation is to make our students aware of fundamental abstracted logical behaviors of future nano-devices, their functionality. This effort would also help the students use their existing knowledge of K-map based logical synthesis into constructing logic blocks for novel devices that uses majority logic as basic construct. Moreover, additional to stimulating our students' interests, we are also augmenting their learning by challenging them to use their existing knowledge to analyze, synthesize and comprehend novel nano-logic issues through the worksheets and lecture modules. Whereas many efforts are focusing on developing new courses on nanofabrication and even nano-computing, we intend to augment the existing standard EE and CS courses by inserting knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework.