A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

T. Rejimon and S. Bhanja, “A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis”, Accepted for publication in IEEE Transactions on VLSI Systems, Volume 14, Issue 10, pp.1130-1139, 2006. (A preliminary version of this paper was nominated for “Best Paper Award” and received “Honorable Mention award” in Intl. Conference of VLSI Design 2006).

@ARTICLE{1715349,
title={A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis},
author={Rejimon, T. and Bhanja, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2006},
month={Oct. },
volume={14},
number={10},
pages={1130-1139},
abstract={With device size shrinking and fast rising frequency ranges, the effect of cosmic radiations and alpha particles known as single-event upset (SEU) and single-event transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of SEU sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure, and gate delays on SEU sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but it also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate nonsimulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time},
keywords={belief networks, integrated circuit modelling, integrated circuit reliability, integrated logic circuits, radiation effectsBayesian inference, Bayesian network, SEU sensitivity, alpha particles effect, circuit structure, cosmic radiations effect, device size, gate delays, logic circuits, logic level design abstraction, radiation tolerant designs, single joint probability distribution function, single-event transients, single-event upset, soft error hardening techniques, timing-aware probabilistic model},
doi={10.1109/TVLSI.2006.884165},
ISSN={1063-8210}, }