Magnetic Cellular Automata

We are interested in Low Energy Computing where computing occurs due to the coupling of the computing elements. In conventional computing, electrons flow from one points to another to process information. In Nano-computing-Resaerch-Group@EE-Univ. of South florida, we pursue a novel cellular automata computing paradigm, where state of the computing elements change and the next computing element couples to the change in the previous computing element and extreme low power dissipation is possible.

We are currently exploring computing with nano-scale soft magnets that are easy to switch, requires no power in the memory state, and can be operated at room temperature. Each magnetic cell is a single domain nano magnet in which all the spins are aligned to one direction. By shape engineering, we can have two dominant state "0" and "1" as shown here. Information processing occurs due to neighbor interactions and there is no physical movement of magnets. In this sense, requirement from Magnetic Cellular automata (MCA) is orthogonal to Magnetic RAM when inter-cell interaction are prohibited. We are however interested in interfacing such systems with MRAM, and sensors providing low energy embedded computing.

In this work, we fabricate nano magnetic structure by E-beam Lithography and observe them qualitatively using Scanning Probe Mucroscope in magnetic mode. So far, varous length of magnetic interconnects, and magnetic crosswires are fabricated.

We have also proposed a spatially moving clocking field for the ordering of the magnets. We are also interested in defect characterization, shape engineering, scaling limits on such devices.

Our recent interest is in creating multi-layer magnetic cells as MQCA elements. We are exploring various clocking and device designs and architectures that can resolve some of the criticism of device integration and low power operation of its previous generation.
We will post a Verilog A model for the cell and architecture shortly once the copyright issues are resolved.

Quantum Cellular Automata

We are interested in Low Energy Computing where computing occurs due to the coupling of the computing elements. In conventional computing, electrons flow from one points to another to process information. In Nano-computing-Resaerch-Group@EE-Univ. of South florida, we pursue a novel cellular automata computing paradigm, where state of the computing elements change and the next computing element couples to the change in the previous computing element and extreme low power dissipation is possible. In Quantum Cellular Automata, each computing cell has four Q-dot and two electrons. Electrons occupy the diagonal Q-dots to minimize the overall energy. Inter-cell barrier confines the electrons in the cell. However, electrons in the neighboring cells allign themselves accroding to the driver cell transfering information. Various cells including a shift register, inverter etc are fabricated and large designs are have been proposed using four phase clocking scheme. We are interested in modeling reliablity, defect, design and power-error trade-offs in Quantum Cellular Automata.

 

Download the QCAPro tool

Reliability Analysis for post-CMOS Devices

We work on probabilistic graph structures like Bayesian Networks to model statistical variability of nano-devices. Note that this problem is not new and huge literature exists on"computing with unreliable components" and bounds.

What changed though from before is the phenomenal error rates simply due to extremely low energy computing requirements that random thermal energy can cause temporary errors. We transform the circuit (shown in Figure) into a probabilistic network which in turn is transformed into a junction tree for local computing advantages.

Problems that we intend to look at are

1. Can we arrive at models driven by the underlying Physics of the devices?
2. What would be best heuristics to track worst case scenario?
3. Error/Defect at the boundaries of integration of various devices.
4. Are we heading back to analog? If so, why not use some of the strength?
5. Can we learn structures successfully in inputs and in defects?

Magnetic Cellular Automata Coplanar Cross Wire Systems

J. Pulecio and S.Bhanja,"Magnetic Cellular Automata Coplanar Cross Wire Systems", Accepted to Nano-DDS (Platform paper, oral), 2009.

Work In Progress - An Education Module on Engineering Ethics Concentrating on Environment-Friendly Engineering for Computer Engineers

K. Lingasubramanian and S. Bhanja, " Work In Progress - An Education Module on Engineering Ethics Concentrating on Environment-Friendly Engineering for Computer Engineers", Accepted for publication in IEEE Frontiers in Education (FIE), 2009

Dr. Bhanja delivers invited Talk in Intl. Workshop on QCA

Dr. Bhanja presents the NCRG's Nano-Electronics research effort in Intl. Workshop on QCA, held in Univ. of British Columbia.

Fast Estimation of Power Dissipation in QCA Circuits

S. Srivastava, S. Sarkar and S. Bhanja, “Estimation of Upper Bound of Power Dissipation in QCA Circuits”, Accepted, IEEE Transactions on Nanotechnology, vol. 8-1, pp. 116--127, 2009. @ARTICLE{4625949, title={Estimation of Upper Bound of Power Dissipation in QCA Circuits}, author={Srivastava, S. and Sarkar, S. and Bhanja, S.}, journal={Nanotechnology, IEEE Transactions on}, year={2009}, month={Jan. }, volume={8}, number={1}, pages={116-127}, abstract={Quantum-dot cellular automata (QCA) is a field-coupled computing paradigm. States of a cell change due to mutual interactions of either electrostatic or magnetic fields. Due to their small sizes, power is an important design parameter. In this paper, we derive an upper bound for power loss that will occur with input change, even with the circuit staying at respective ground states before and after the change. This bound is computationally efficient to compute for large QCA circuits since it just requires the knowledge of the before and after ground states due to input change. We categorize power loss in clocked QCA circuits into two types that are commonly used in circuit theory: switching power and leakage power. Leakage power loss is independent of input states and occurs when the clock energy is raised or lowered to depolarize or polarize a cell. Switching power is dependent on input combinations and occurs at the instant when the cell actually changes state. Total power loss is controlled by changing the rate of change of transitions in the clocking function. Our model provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in nonadiabatic operations and gives us the upper bound of power expended. We derive expressions for upper bounds of switching and leakage power that are easy to compute. Upper bounds obviously are pessimistic estimates, but are necessary to design robust circuits, leaving room for operational manufacturing variability. Given that thermal issues are critical to QCA designs, we show how our model can be valuable for QCA design automation in multiple ways. It can be used to quickly locate potential thermal hot spots in a QCA circuit. The model can also be used to correlate power loss with different input vector switching; power loss is dependent on the input vector. We can study the tradeoff between switching and leakage power in QCA circuits. And, we can use the model to vet different designs of the - - same logic, which we demonstrate for the full adder.}, keywords={cellular automata, ground states, integrated circuit design, quantum dotsQCA circuits, clock energy, ground states, leakage power, power dissipation, power loss, quantum-dot cellular automata, switching power, upper bound estimation}, doi={10.1109/TNANO.2008.2005408}, ISSN={1536-125X}, }

 

Download the QCAPro tool

Probabilistic Error Model for Nano-Domain Logic Circuits

T. Rejimon, K. Lingasubramanian and S. Bhanja, “Probabilistic Error Model for Nano-Domain Logic Circuits”, Accepted, IEEE Transactions on VLSI, 2008.

@ARTICLE{4703183,
title={Probabilistic Error Modeling for Nano-Domain Logic Circuits},
author={Rejimon, T. and Lingasubramanian, K. and Bhanja, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2009},
month={Jan. },
volume={17},
number={1},
pages={55-65},
abstract={In nano-domain logic circuits, errors generated are transient in nature and will arise due to the uncertainty or the unreliability of the computing element itself. This type of errors - which we refer to as dynamic errors - are to be distinguished from traditional faults and radiation related errors. Due to these highly likely dynamic errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic. We propose a probabilistic error model based on Bayesian networks to estimate this expected output error probability, given dynamic error probabilities in each device since this estimate is crucial for nano-domain circuit designers to be able to compare and rank designs based on the expected output error. We estimate the overall output error probability by comparing the outputs of a dynamic error-encoded model with an ideal logic model. We prove that this probabilistic framework is a compact and minimal representation of the overall effect of dynamic errors in a circuit. We use both exact and approximate Bayesian inference schemes for propagation of probabilities. The exact inference shows better time performance than the state-of-the art by exploiting conditional independencies exhibited in the underlying probabilistic framework. However, exact inference is worst case NP-hard and can handle only small circuits. Hence, we use two approximate inference schemes for medium size benchmarks. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results. We have performed our experiments on ISCAS'85 and MCNC benchmark circuits. We explore our probabilistic model to calculate: 1) error sensitivity of individual gates in a circuit; 2) compute overall exact error probabilities for small circuits; 3) compute approximate error probabilities for medium sized benchmarks using two stochastic sampling schemes; 4) compare and vet design with respect to dynamic errors; 5) characterize the input space for desired output characteristics by utilizing the unique backtracking capability of Bayesian networks (inverse problem); and 6) to apply selective redundancy to highly sensitive nodes for error tolerant designs.},
keywords={belief networks, error statistics, inference mechanisms, logic CAD, logic circuits, logic gates, network synthesisBayesian inference schemes, Bayesian networks, dynamic error-encoded model, error sensitivity, error tolerant designs, logic gates, nano-domain computing, nano-domain logic circuits, output error probability, probabilistic error modeling, radiation related errors, stochastic sampling schemes},
doi={10.1109/TVLSI.2008.2003167},
ISSN={1063-8210}, }

Dr. Bhanja receives promotion to Associate Professor

Dr. Bhanja gets promoted to Associated Professor with Tenure.

CNT logic knowledge module integrated in digital CMOS logic design

A. Kumari and S. Bhanja, "CNT logic knowledge module integrated in digital CMOS logic design", IEEE Microelectronics Semiconductor Education, 2009

Magnetic Cellular Automata (MCA) arrays under spatially varying field

Magnetic Cellular Automata (MCA) arrays under spatially varying field Kumari, A. Bhanja, S. Electr. Eng. Dept., Univ. of South Florida, Tampa, FL, USA This paper appears in: Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE Publication Date: 2-5 June 2009 On page(s): 50 - 53 Location: Traverse City, MI ISBN: 978-1-4244-4695-7 Digital Object Identifier: 10.1109/NMDC.2009.5167567 Current Version Published: 2009-07-21

Abstract Magnetic Cellular Automata (MCA) is a variant of Quantum-dot-cellular automata (QCA) where neighboring single-domain nano-magnets (also termed as magnetic cell) process and propagate information (logic 1 or logic 0) through mutual interaction. The attractive nature of this framework is that not only room temperature operations are feasible but also interaction between neighbors is central to information processing as opposed to creating interference. In this work, we explore spatially moving Landauer clocking scheme for MCA arrays (length of eight, sixteen and thirty-two cells) and show the role and effectiveness of the clock in propagating logic signal from input to output without magnetic frustration. Simulation performed in OOMMF.

Magnetic Cellular Automata wires

Magnetic Cellular Automata wires

Pulecio, J.F. Bhanja, S.
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
This paper appears in: Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE
Publication Date: 2-5 June 2009
On page(s): 73 - 75
Location: Traverse City, MI
ISBN: 978-1-4244-4695-7
Digital Object Identifier: 10.1109/NMDC.2009.5167576
Current Version Published: 2009-07-21
Abstract
Magnetic Cellular Automata (MCA) is a novel take on an alternative technological actualization of Boolean logic machines. Not only has it been able to prototypically demonstrate successful operation of logical gates at room temperature; all key components necessary to implement any Boolean function has been realized. We present work further reducing the size of the single domain nano-magnet, approximately 100 times 50 times 30 nm, and physically implement two types of MCA wire architectures ferromagnetic and anti-ferromagnetic. We report the first physical implementation of shape engineered ferromagnetic wires and compare both wires under saturating magnetic fields in the Z direction. We have concluded experimentally, that for conventional data propagation between logical networks, ferromagnetic wires provide extremely stable operation. The high order of coupling we found under saturating magnetic fields demonstrates the flexible clocking nature of ferromagnetic wires and inches the technology closer to implementing complex circuitry.

Invited Paper in IEEE NMDC, 2009

Anita Kumari's work published in IEEE NMDC gets accepted as Invited Paper, 2009

Dr. Bhanja is selected as Program Co-Chair, IEEE ISVLSI, 2009

Dr. Bhanja was selected as Technical Program Co-chair for IEEE ISVLSI, 2009

General Co-chair

Dr. Bhanja was selected as General Co-chair, ACM GLSVLSI 2009

Defect characterization in magnetic field coupled arrays

Defect characterization in magnetic field coupled arrays Kumari, A. Pulecio, J.F. Bhanja, S. Electr. Eng. Dept., Univ. of South Florida, Tampa, FL This paper appears in: Quality of Electronic Design, 2009. ISQED 2009. Quality of Electronic Design Publication Date: 16-18 March 2009 On page(s): 436 - 441 Location: San Jose, CA ISBN: 978-1-4244-2952-3 Digital Object Identifier: 10.1109/ISQED.2009.4810334 Current Version Published: 2009-04-03

Abstract Magnetic Cellular Automata (MCA) utilizes mutual exchange energies of neighboring magnetic cells to order the single-domain magnetic cell which in turn performs computational tasks. In this paper, we study three dominant type of geometric defects (missing, spacing, merging) in array (used as interconnects) based on our fabrication experiments. We study effect of these defects in three segments of the array (near-input, center and near-output) and we have observed that location of these defects play an important role in masking of the errors. The observed simulation results indicate that most of the defects occurring around center and near-output would be masked generating correct behavior while defects in the near-input segment would mostly cause erroneous output. We also observe that MCA is extremely robust towards space irregularities, one of the most common form of defect we observed through our fabrication techniques.

An Error Model to Study the Behavior of Transient Errors in Sequential Circuits

An Error Model to Study the Behavior of Transient Errors in Sequential Circuits Lingasubramanian, K. Bhanja, S. Nano Comput. Res. Group (NCRG), Univ. of South Florida, Tampa, FL This paper appears in: VLSI Design, 2009 22nd International Conference on Publication Date: 5-9 Jan. 2009 On page(s): 485 - 490 Location: New Delhi ISSN: 1063-9667 ISBN: 978-0-7695-3506-7 Digital Object Identifier: 10.1109/VLSI.Design.2009.73 Current Version Published: 2009-01-19

Abstract In sequential logic circuits the transient errors that occur in a particular time frame will propagate to consecutive time frames thereby making the device more vulnerable. In this work we propose a probabilistic error model for sequential logic that can measure the expected output error probability, given a probabilistic input space, that account for both spatial dependencies and temporal correlations across the logic, using a time evolving causal network. We demonstrate our error model using MCNC and ISCAS benchmark circuits and validate it with HSpice simulations. Our observations show that, significantly low individual gate error probabilities produce at least 5 fold higher output error probabilities. The average error percentage of our results with reference to HSpice simulation results is only 4.43%. Our observations show that the order of temporal dependency of error varies for different sequential circuits.