Reliability Analysis for post-CMOS Devices

We work on probabilistic graph structures like Bayesian Networks to model statistical variability of nano-devices. Note that this problem is not new and huge literature exists on"computing with unreliable components" and bounds.

What changed though from before is the phenomenal error rates simply due to extremely low energy computing requirements that random thermal energy can cause temporary errors. We transform the circuit (shown in Figure) into a probabilistic network which in turn is transformed into a junction tree for local computing advantages.

Problems that we intend to look at are

1. Can we arrive at models driven by the underlying Physics of the devices?
2. What would be best heuristics to track worst case scenario?
3. Error/Defect at the boundaries of integration of various devices.
4. Are we heading back to analog? If so, why not use some of the strength?
5. Can we learn structures successfully in inputs and in defects?