Probabilistic Maximum Error Modeling for Unreliable Logic Circuits

K. Lingasubramanian and S.Bhanja, “Probabilistic Maximum Error Modeling for Unreliable Logic Circuits”, Accepted for publication in ACM Great Lake Symposium on VLSI, 2007.

@conference{lingasubramanian2007probabilistic,
title={{Probabilistic maximum error modeling for unreliable logic circuits}},
author={Lingasubramanian, K. and Bhanja, S.},
booktitle={Proceedings of the 17th ACM Great Lakes symposium on VLSI},
pages={223--226},
year={2007},
organization={ACM New York, NY, USA}
}