A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity

T. Rejimon and S. Bhanja, “A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity”, Accepted for publication in IEEE Intl. Conference on VLSI Design, 2006 (Nominated for “Best Paper Award” and received “Honorable mention award”).

@INPROCEEDINGS{1581439,
title={A stimulus-free probabilistic model for single-event-upset sensitivity},
author={Thara Rejimon and Sanjukta Bhanja},
booktitle={VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on},
year={2006},
month={Jan.},
volume={},
number={},
pages={ 8 pp.-},
abstract={ With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as single-event-upset (SEU), is a growing concern in logic circuits. Accurate understanding and estimation of single-event-upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to study the effect of inputs, circuit structure and delay on single-event-upset sensitivity of nodes in logic circuits as a single joint probability distribution function (PDF). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint PDF which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.},
keywords={ belief networks, integrated circuit design, logic circuits, logic design, radiation hardening (electronics), statistical distributions Bayesian network, PDF, SEU, benchmark circuits, directional graph, exponential complexity, logic circuits, logic level design abstraction, probability distribution function, single-event-upset sensitivity, smart probabilistic inference, soft error hardening techniques, stimulus-free inference, stimulus-free probabilistic model},
doi={10.1109/VLSID.2006.26},
ISSN={1063-9667}, }