Pinning fault mode modeling for DWM shifting

 Roxy, K., Longofono, S., Olliver, S., Bhanja, S., & Jones, A. K. (2022). Pinning fault mode modeling for DWM shifting. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(7), 3319-3323.

Abstract:

Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults arise when aligning domains with access points. A previously understudied type of shifting fault, a pinning fault may occur due to non-uniform pinning potential distribution caused by notches with fabrication imperfections. This non-uniformity can pin a wall during current-induced DW motion. This brief provides a model of geometric variations varying width, depth, and curvature variations of a notch, their impacts on the critical shift current, and a study of the resulting impact on fault rates of DW memory systems. An increase in the effective critical shift current due to 5% variation predicts a pinning fault rate on the order of 10 ^-8 per shift. This results in a mean-time-to-failure (MTTF) of circa 2s for a DW memory system and requires multi-bit error correction for achieving reasonable system lifetimes.