WIP- Dominant Sensory Mode based Groups in VLSI Classes

S. Bhanja, “WIP- Dominant Sensory Mode based Groups in VLSI Classes”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2006.

@conference{bhanja2006work,
title={{Work in Progress: Dominant Sensory Mode based Groups in VLSI Classes}},
author={Bhanja, S.},
booktitle={Frontiers in Education Conference, 36th Annual},
pages={14--15},
year={2006}
}

Abstract:


This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class. Our motivation is to make our students aware of fundamental abstracted logical behaviors of future nano-devices, their functionality. This effort would also help the students use their existing knowledge of K-map based logical synthesis into constructing logic blocks for novel devices that uses majority logic as basic construct. Moreover, additional to stimulating our students' interests, we are also augmenting their learning by challenging them to use their existing knowledge to analyze, synthesize and comprehend novel nano-logic issues through the worksheets and lecture modules. Whereas many efforts are focusing on developing new courses on nanofabrication and even nano-computing, we intend to augment the existing standard EE and CS courses by inserting knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework.

VLSI DESIGN Honorable Mention Award

Probabilistic model on soft error paper (Thara Rejimon, Sanjukta Bhanja) was nominated for "Best Paper award" and received "Honorable Mention" award in IEEE Conference on Vlsi Design 2006.

Javier Pulecio receives BD Scholarship

Javier Pulecio receives National Science Foundation Bridge to Doctorate scholarship.

Dr. Ottavi's visit

Dr. Marco Ottavi delivers invited lecture on QCA Circuits

DAC YSSP

Javier Pulecio Receives Young Student Support Scholarship to attend DAC 2005

A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC

V. K. Jain, S. Bhanja, G. H. Chapman, L. Doddannagari and N. Nguyen, “A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC”, Accepted for publication for IEEE SOC conference, pp. 243-246, 2005.

@INPROCEEDINGS{1554503,
title={A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC},
author={Jain, V.K. and Bhanja, S. and Chapman, G.H. and Doddannagari, L.},
booktitle={SOC Conference, 2005. Proceedings. IEEE International},
year={2005},
month={Sept.},
volume={},
number={},
pages={ 243-246},
abstract={A 3D heterogeneous system on a chip using a stack of planes has recently been proposed. While the sensors are located on the top plane, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on a reconfigurable computing array for its DSP plane. The advantages of such an approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. The authors presented the reconfigurable J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA_PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the benefits of reduced external interconnect, much reduced design time, and manageable testability. The paper discusses these cells, including a new concept, namely multi-granularity. The methodology for mapping algorithms is illustrated by two important examples, FIR filtering of signals and images and the independent component analysis (ICA) algorithm. Finally, the paper discusses the issue of defect tolerance, which is critical in attaining reasonable yields making chip manufacture feasible.},
keywords={ VLSI, digital signal processing chips, reconfigurable architectures, system-on-chip 3D heterogeneous system-on-chip, DSP plane, coarse grain VLSI cells, data fabric cell, defect tolerance, extended multiply accumulate cell, independent component analysis, reconfigurable J-platform, reconfigurable computing array, universal nonlinear cell},
doi={10.1109/SOCC.2005.1554503},
ISSN={}, }

Scalable Probabilistic Computing Models using Bayesian Networks

T. Rejimon and S. Bhanja, “Scalable Probabilistic Computing Models using Bayesian Networks”, Accepted for IEEE Intl. Midwest Symposium on Circuits and Systems (MWSCAS), pp. 712-715, 2005.

@INPROCEEDINGS{1594200,
title={Scalable probabilistic computing models using Bayesian networks},
author={Rejimon, T. and Bhanja, S.},
booktitle={Circuits and Systems, 2005. 48th Midwest Symposium on},
year={2005},
month={Aug.},
volume={},
number={},
pages={712-715 Vol. 1},
abstract={As technology scales below 100nm and operating frequencies increase, correct operation of nano-CMOS will be compromised due reduced device-to-device distance, imperfections, and low noise and voltage margins. Unlike traditional faults and defects, these errors are expected to be transient in nature. Unlike radiation related upset errors, the propensity of these transient errors will be higher. Due to these highly likely errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic events. We propose the formalism of probabilistic Bayesian networks (BNs), which also forms a complete joint probability model, for probabilistic computing. Using the exact probabilistic inference scheme known as clustering, we show that for a circuit with about 250 gates the output error estimation time is less than three seconds on a 2GHz processor. This is three orders of magnitude faster than a recently proposed method for probabilistic computing using transfer matrices},
keywords={belief networks, errors, logic gates, microcomputers, probabilistic logic, probability, transients2 GHz, Bayesian networks, device-to-device distance, low noise margins, nano-CMOS operation, nanodomain computing, scalable probabilistic computing, transfer matrices, transient errors, voltage margins},
doi={10.1109/MWSCAS.2005.1594200},
ISSN={}, }