Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits

S. Srivastava, S. Sarkar and S. Bhanja, “Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits”, Accepted for publication in IEEE conference on nanotechnology, Cincinnati, 2006. @INPROCEEDINGS{1717105, title={Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits}, author={ Srivastava, S. and Sarkar, S. and Bhanja, S.}, booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on}, year={2006}, month={June}, volume={1}, number={}, pages={ 375-378}, abstract={ The goal of this work is to present a worst-case power estimation model for QCA designs. Based on existing power models, we derive upper bound for power dissipation that occurs for non-adiabatic clock switching and represents the worst-case power estimate. This upper bound is easy to compute and does not require simulation of quantum dynamics. Given the criticality of thermal issues and the inherent process variabilities at nano-scale, such worst case estimates, that is easy to compute, will be useful at higher levels of design abstractions, so as to vet different designs or to create power macromodels for different circuit components. There are three power dissipation events for each cell: first when the clock goes up, second when the input switches, and third when the clock goes down. The first and the third events are analogous to “leakage” power in CMOS designs in that there is dissipation even when there is no change in inputs. The second event can be related to “switching” power in CMOS and is dependent on inputs. The proportion between these two types of dissipations is strongly dependent on the clock energy. In addition to the clock, the other determining factors are cell polarization, kink energy, and quantum relaxation time. We demonstrate the model using majority gate and inverter, which are critical circuit components.}, doi={}, ISSN={}, }

 

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Switching Error Modes of QCA Circuits

S. Bhanja and S. Sarkar, “Switching Error Modes of QCA Circuits”, Accepted for publication in IEEE conference on nanotechnology, Cincinnati, 2006.

@INPROCEEDINGS{1717107,
title={Switching Error Modes of QCA Circuits},
author={ Bhanja, S. and Sarkar, S.},
booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on},
year={2006},
month={June},
volume={1},
number={},
pages={ 383-386},
abstract={ The Quantum-dot Cellular Automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a collection of QCA cells, with two possible ground states for each cell. A four phased clocking is used to keep the computations at the ground state throughout the circuit. Computing errors in QCA circuits can arise due to the failure of the clocking scheme to switch portions of the circuit to its new ground state with change in input. To study these switching errors we need to consider low-energy state configurations of QCA circuits. However, current QCA simulators compute just the ground state configuration of a QCA arrangement. In this paper, we offer an efficient method, based on graphical probabilistic models, to compute the N-lowest energy modes of a clocked QCA circuit. The overall low-energy, excited, spectrum of multiple clocking zones is constructed by concatenating the excited spectra of the individual clocking zones. We demonstrate the use of this error model by comparing different designs of wire crossings.},
doi={},
ISSN={}, }

Bayesian Macromodeling for Circuit Level QCA Design

S. Srivastava and S. Bhanja, “Bayesian Macromodeling for Circuit Level QCA Design”, Accepted for publication in IEEE conference on nanotechnology, Cincinnati, 2006.

@INPROCEEDINGS{1717009,
title={Bayesian Macromodeling for Circuit Level QCA Design},
author={ Srivastava, S. and Bhanja, S.},
booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on},
year={2006},
month={June},
volume={1},
number={},
pages={ 31-34},
abstract={ We present a probabilistic methodology to model and abstract the behavior of quantum-dot cellular automata circuit(QCA) at “ circuit level” above the current practice of layout level. These macromodels provide input-output relationship of components (a set of QCA cells emulating a logical function) that are faithful to the underlying quantum effects. We show the macromodeling of a few key circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners. In this work, we demostrate how we can make use of these macromodels to abstract the logical function of QCA circuits and to extract crucial device level characteristics such as polarization and low-energy error state configurations by circuit level Bayesian model, accurately accounting for temperature and other device level parameters. We also demonstrate how this macromodel based design can be used effectively in analysing and isolating the weak spots in the design at circuit level itself.},
doi={},
ISSN={}, }

Probabilistic Error Model for Unreliable Nano-Logic gates

T. Rejimon and S. Bhanja, “Probabilistic Error Model for Unreliable Nano-Logic gates”, Accepted for publication in IEEE conference on nanotechnology, pp. Cincinnati, 2006.

@INPROCEEDINGS{1717013,
title={Probabilistic Error Model for Unreliable Nano-logic Gates},
author={ Rejimon, T. and Bhanja, S.},
booktitle={Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on},
year={2006},
month={June},
volume={1},
number={},
pages={ 47-50},
abstract={ We propose a novel formalism, based on probabilistic Bayesian networks, to capture, analyze, and model dynamic errors at nano logic for probabilistic reliability analysis. It will be important for circuit designers to be able to compare and rank designs based on the expected output error, which is a measure of reliability. We propose an error model to estimate this expected output error probability, given the probability of these errors in each device. We estimate the overall output error probability by comparing the outputs of an ideal logic model with a dynamic error-encoded model. We use of Bayesian inference schemes for propagation of probabilities. Since exact inference is worst case NP-hard, we use two approximate inference schemes based on importance sampling, namely EPIS(Evidence Prepropagated Importance Sampling) and PLS (Probabilistic Logic Sampling), for handling mid-size benchmarks having up to 3500 gates. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results.},
doi={},
ISSN={}, }

Novel Designs for Thermally Robust Coplanar Crossing in QCA

S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi, “Novel Designs for Thermally Robust Coplanar Crossing in QCA”, Accepted for publication in IEEE Design Automation and Test in Europe (DATE), pp. 786-791, 2006.

@INPROCEEDINGS{1656996,
title={Novel designs for thermally robust coplanar crossing in QCA},
author={Bhanja, S. and Ottavi, M. and Lombardi, F. and Pontarelli, S.},
booktitle={Design, Automation and Test in Europe, 2006. DATE '06. Proceedings},
year={2006},
month={March},
volume={1},
number={},
pages={6 pp.-},
abstract={In this paper, different circuit arrangements of quantum-dot cellular automata (QCA) are proposed for the so-called coplanar crossing. These arrangements exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. Using a Bayesian network (BN) based simulator, new results are provided to evaluate the robustness to so-called kink of these arrangements to thermal variations. The BN simulator provides fast and reliable computation of the signal polarization versus normalized temperature. It is shown that by modifying the layout, a higher polarization level can be achieved in the routed signal by utilizing the proposed QCA arrangements},
keywords={Bayes methods, cellular automata, logic design, quantum computing, quantum dotsBayesian network based simulator, Cartesian plane, majority voting properties, quantum-dot cellular automata, signal polarization, thermal variations, thermally robust coplanar crossing, wire crossing},
doi={10.1109/DATE.2006.244120},
ISSN={}, }

A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity

T. Rejimon and S. Bhanja, “A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity”, Accepted for publication in IEEE Intl. Conference on VLSI Design, 2006 (Nominated for “Best Paper Award” and received “Honorable mention award”).

@INPROCEEDINGS{1581439,
title={A stimulus-free probabilistic model for single-event-upset sensitivity},
author={Thara Rejimon and Sanjukta Bhanja},
booktitle={VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on},
year={2006},
month={Jan.},
volume={},
number={},
pages={ 8 pp.-},
abstract={ With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as single-event-upset (SEU), is a growing concern in logic circuits. Accurate understanding and estimation of single-event-upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to study the effect of inputs, circuit structure and delay on single-event-upset sensitivity of nodes in logic circuits as a single joint probability distribution function (PDF). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint PDF which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.},
keywords={ belief networks, integrated circuit design, logic circuits, logic design, radiation hardening (electronics), statistical distributions Bayesian network, PDF, SEU, benchmark circuits, directional graph, exponential complexity, logic circuits, logic level design abstraction, probability distribution function, single-event-upset sensitivity, smart probabilistic inference, soft error hardening techniques, stimulus-free inference, stimulus-free probabilistic model},
doi={10.1109/VLSID.2006.26},
ISSN={1063-9667}, }

Probabilistic Modeling of QCA Circuits using Bayesian Networks

S. Bhanja and S. Sarkar, “Probabilistic Modeling of QCA Circuits using Bayesian Networks”, Accepted for publication in IEEE transaction on Nanotechnology, Volume 5, Issue 6, pp. 657 – 670, 2006.

@ARTICLE{4011919,
title={Probabilistic Modeling of QCA Circuits Using Bayesian Networks},
author={Bhanja, S. and Sarkar, S.},
journal={Nanotechnology, IEEE Transactions on},
year={2006},
month={Nov. },
volume={5},
number={6},
pages={657-670},
abstract={To push the frontiers of quantum-dot cellar automata (QCA) based circuit design, it is necessary to have design and analysis tools at multiple levels of abstractions. To characterize the performance of QCA circuits it is not sufficient to specify just the binary discrete states (0 or 1) of the individual cells, but also the probabilities of observing these states. We present an efficient method based on graphical probabilistic models, called Bayesian networks (BNs), to model these steady-state cell state probabilities, given input states. The nodes of the BN are random variables, representing individual cells, and the links between them capture the dependencies among them. BNs are minimal, factored, representation of the overall joint probability of the cell states. The method is fast and its complexity is shown to be linear in terms of the number of cells. This BN model allows us to analyze clocked QCA circuits in terms of quantum- mechanical quantities, such as steady-state polarization and thermal ratios for each cell, without the need for full quantum-mechanical simulation, which is known to be very slow and is best postponed to the final stages of the design process. We can also estimate the most likely (or ground) state configuration for all the cells and the lowest energy configuration that results in output errors. We validate the model with steady-state probabilities computed by the Hartree-Fock self-consistent approximation (HT-SCA). Using full adder designs, we demonstrate the ability to compare and contrast QCA circuit designs with respect to the variation of the output state probabilities with temperature and input. We also show how weak spots in clocked QCA circuit designs can be found using our model by comparing the (most likely) ground-state configuration with the next most likely energy state configuration that results in output error},
keywords={Bayes methods, HF calculations, SCF calculations, cellular automata, logic circuits, logic design, nanotechnology, network synthesis, probability, semiconductor quantum dotsBayesian networks, Hartree-Fock self-consistent approximation, Markov models, QCA circuits, binary discrete states, circuit design, energy state configuration, full adder designs, ground-state configuration, nanocomputing, nanotechnology, probabilistic modeling, quantum-dot cellular automata, quantum-mechanical simulation, steady-state cell state probability, steady-state polarization, stochastic logic circuits},
doi={10.1109/TNANO.2006.883474},
ISSN={1536-125X}, }

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

T. Rejimon and S. Bhanja, “A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis”, Accepted for publication in IEEE Transactions on VLSI Systems, Volume 14, Issue 10, pp.1130-1139, 2006. (A preliminary version of this paper was nominated for “Best Paper Award” and received “Honorable Mention award” in Intl. Conference of VLSI Design 2006).

@ARTICLE{1715349,
title={A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis},
author={Rejimon, T. and Bhanja, S.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2006},
month={Oct. },
volume={14},
number={10},
pages={1130-1139},
abstract={With device size shrinking and fast rising frequency ranges, the effect of cosmic radiations and alpha particles known as single-event upset (SEU) and single-event transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of SEU sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure, and gate delays on SEU sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but it also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate nonsimulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time},
keywords={belief networks, integrated circuit modelling, integrated circuit reliability, integrated logic circuits, radiation effectsBayesian inference, Bayesian network, SEU sensitivity, alpha particles effect, circuit structure, cosmic radiations effect, device size, gate delays, logic circuits, logic level design abstraction, radiation tolerant designs, single joint probability distribution function, single-event transients, single-event upset, soft error hardening techniques, timing-aware probabilistic model},
doi={10.1109/TVLSI.2006.884165},
ISSN={1063-8210}, }

A Stimulus-free Graphical Probabilistic Switching Model for Sequential Circuits using Dynamic Bayesian Networks

S. Bhanja, K. Lingasubramanian and N. Ranganathan, “A Stimulus-free Graphical Probabilistic Switching Model for Sequential Circuits using Dynamic Bayesian Networks” Accepted for publication in ACM Transactions on Design Automation and Electronic System, Volume 11, Issue 3, pp. 773-796, 2006.

@article{bhanja2006stimulus,
title={{A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks}},
author={Bhanja, S. and Lingasubramanian, K. and Ranganathan, N.},
journal={ACM Transactions on Design Automation of Electronic Systems (TODAES)},
volume={11},
number={3},
pages={773--796},
year={2006},
publisher={ACM New York, NY, USA}
}

WIP- Dominant Sensory Mode based Groups in VLSI Classes

S. Bhanja, “WIP- Dominant Sensory Mode based Groups in VLSI Classes”, accepted for publication in 36^th ASEE/IEEE Frontiers in Education (FIE), 2006.

@conference{bhanja2006work,
title={{Work in Progress: Dominant Sensory Mode based Groups in VLSI Classes}},
author={Bhanja, S.},
booktitle={Frontiers in Education Conference, 36th Annual},
pages={14--15},
year={2006}
}

Abstract:


This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class. Our motivation is to make our students aware of fundamental abstracted logical behaviors of future nano-devices, their functionality. This effort would also help the students use their existing knowledge of K-map based logical synthesis into constructing logic blocks for novel devices that uses majority logic as basic construct. Moreover, additional to stimulating our students' interests, we are also augmenting their learning by challenging them to use their existing knowledge to analyze, synthesize and comprehend novel nano-logic issues through the worksheets and lecture modules. Whereas many efforts are focusing on developing new courses on nanofabrication and even nano-computing, we intend to augment the existing standard EE and CS courses by inserting knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework.

VLSI DESIGN Honorable Mention Award

Probabilistic model on soft error paper (Thara Rejimon, Sanjukta Bhanja) was nominated for "Best Paper award" and received "Honorable Mention" award in IEEE Conference on Vlsi Design 2006.