Nanomagnetic Logic For Low Energy High Density Circuits (Accepted IEEE Trans on VLSI 2013)

@ARTICLE{TVLSI_Das, 

author={Das, J. and Alam, S.M. and Bhanja, S.}, 

journal={VLSI Systems I: Regular Papers, IEEE Transactions on}, 

title={Nanomagnetic Logic For Low Energy High Density Circuits}, 

year={2013}, 

month={}, 

volume={}, 

number={}, 

pages={}, 

keywords={logic-in-memory, spintronic, nanomagnetic, low energy, MTJ, EDP, high density logic.}, 

doi={}, 

ISSN={},

notes-={Accepted},}

Dr. Bhanja was Symposium Co-chair for NanoForida 2012

Dr. Bhanja delivers invited talk NC-LSAMP conference, September 2012

Sanjukta Bhanja, "Disciplines Without Border: Experiential Perspective" Invited Talk, @ NC-LSAMP conference NC A&T, September 2012.

Dr. Bhanja delivers Invited talk in DAC Young Faculty Mentoring workshop, 2012

Dr. Bhanja Invited to NSF CAREER Award Mentoring workshop, May 2012

Dr. Bhanja delivers invited talk in NSF CISE CAREER mentoring workshop, Arizona State University, May 2012.

Book Chapter:Nanoelectronic Device Applications Handbook

J. Pulecio, S. Sarkar and S. Bhanja, “An Experimental Demonstration of the Viability of Energy
Minimizing Computing using Nano-magnets” in “Nanoelectronic Device Applications
Handbook”, edited by James Morris & Krzysztof Iniewski, CRC Press (Taylor & Francis Group),
2012.

Book Chapter:Nanoelectronic Device Applications Handbook

J. Das, S. M. Alam and S. Bhanja, “Non-volatile Logic-in-Memory Architecture: An Integration
between Nanomagnetic Logic and Magneto-resistive RAM” in “Nanoelectronic Device
Applications Handbook”, edited by James Morris & Krzysztof Iniewski, CRC Press (Taylor &
Francis Group), 2012.

Book Chapter: Test, Defect Tolerance and Reliability for Emerging Nanotechnologies

S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi, “QCA Circuits for Robust Coplanar
Crossing”, in “Test, Defect Tolerance and Reliability for Emerging Nanotechnologies”, edited
by Mohammad Tehranipoor, Springer Science +Business Media, LLC, 2008.

Effectiveness of Knowledge Module on “Intel 45 nm Transistor and High-k Dielectric” into Undergraduate Semiconductor Devices Course (IEEE IEDEC 2012)

C. Siyambalapitiya, R. Hyde, K. Kusmierek and S.Bhanja, “Effectiveness of Knowledge
Module on “Intel 45 nm Transistor and High-k Dielectric” into Undergraduate Semiconductor
Devices Course”, Accepted for IEEE 2nd Interdisciplinary Engineering Design Education Conference
(IEDEC), 2011.

Non-Destructive Variability Tolerant Differential Read for Non-Volatile Logic (IEEE MWSCAS, 2012)

J. Das, S. M. Alam and S. Bhanja, “Non-Destructive Variability Tolerant Differential Read for
Non-Volatile Logic”, Accepted for IEEE 55th Int'l Midwest Symposium on Circuits & Systems,
2012.

Evaluation of Circuit Styles and VLSI Logic Designs of Pentacene OTFTs (IEEE MWSCAS, 2012)

S. Mishra and S. Bhanja, “Evaluation of Circuit Styles and VLSI Logic Designs of Pentacene
OTFTs”, Accepted for IEEE 55th Int'l Midwest Symposium on Circuits & Systems, 2012.

Addressing The Layout Constraint Problem in Cascading Logic Gates in Nanomagnetic Logic (IEEE Nano 2012)

J. Das, S. M. Alam and S. Bhanja, “Addressing The Layout Constraint Problem in Cascading
Logic Gates in Nanomagnetic Logic”, Accepted for IEEE Conference on Nanotechnology, 2012

A Novel Design Concept for High Density Hybrid CMOSNanomagnetic Circuits (IEEE Nano 2012)

J. Das, S. M. Alam and S. Bhanja, “A Novel Design Concept for High Density Hybrid CMOSNanomagnetic
Circuits”, Accepted for IEEE Conference on Nanotechnology, 2012

Study of Multilayer Spintronic Devices for Logic Computation (Intermag 2012)

S. Rajaram, D. Karunaratne and S. Bhanja, “Study of Multilayer Spintronic Devices for Logic
Computation”, IEEE INTERMAG, 2012.

Ultra-low Power Hybrid CMOS-Magnetic Logic Architecture (IEEE Trans on CAS, 2012)

J. Das, S. M. Alam and  S. Bhanja, "Ultra-low Power Hybrid CMOS-Magnetic LogicArchitecture", Accepted for IEEE Transactions on Circuits and Systems, 2012.

Abstract:

Magnetic coupling between single layer nanomagnets is
used to realize magnetic logic. Apart from writing and reading,
one other phenomenon performed on the magnets is
clocking. Traditionally, these operations were carried out using
external magnetic fields generated by current carrying
conductors. But the current requirements are typically in mA
which increases the overall power. Also, the fields cannot be
sharply terminated at the boundary between two nanomagnets
which needs to be clocked at two different instants. The above
concerns motivated us to look into alternate magnetic devices
to realize magnetic logic. We suggested the use of multilayer
spintronic devices (the Magnetic Tunnel Junctions abbr.
MTJs) for carrying out logic computation. MTJs are already
in use in magnetic-MRAMs from where we have borrowed
some concepts in writing and reading our logic. The MTJ
free layers are capable of interacting with neighbors through
magnetic coupling. We have proposed the use of this coupling
to compute logic in this paper. At the same time, MTJs also
provide scope for CMOS integration which we have used
to assist in current driven writing, clocking and reading the
devices. CMOS integration also improves the overall control
over individual cells in the logic. In this paper we have
presented a novel CMOS integrated MTJ architecture layout
that enables (a) logic computation using magnetic coupling
between MTJs and (b) current driven input, clock and read
operations that are much more energy efficient. A feasibility
study of this integration in 22nm CMOS node is presented
in the paper along with a variability tolerant reading scheme
for the logic. The proposed architecture achieves over 95%
reduction in energy as seen in various adders and array multiplier
over traditional magnetic logic with external field-based
clocking.

Study of single layer and multilayer nano-magnetic logic architectures (JAP-2012)

Karunaratne, D. K.; Bhanja, Sanjukta; , "Study of single layer and multilayer nano-magnetic logic architectures," Journal of Applied Physics , vol.111, no.7, pp.07A928-07A928-3, Apr 2012
doi: 10.1063/1.3676052
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6164057&isnumber=6146259

Abstract:

 Nano-magnetic logic (NML) has been a promising technology for logic computation. Contribution
of this paper is two-fold. First, we have fabricated and captured MFM images of a NML architecture
that has computed the majority of seven variables. This logic block can potentially implement eight
different logic functions that could be configured in real-time. Next, we have performed a set of
experiments with a multilayer stack of Co/Cu/NiFe with a perpendicular
magnetic anisotropy bottom layer to realize neighbor interaction between adjacent free layers of
devices. Based on the MFM images, we conclude that dipolar coupling between the free layers of
the neighboring spin-valve based NML (SVBN) devices can be exploited to construct local
elements such as majority gates, inverters and interconnects. Since magnetic multilayer stacks have
already been implemented in memory devices to read/write data, SVBN devices would not only
solve the input/output problems in NML but also would have potential in logic-in-memory
applications.VC 2012 American Institute of Physics. [doi:10.1063/1.3676052]

Javier Pulecio receives Outstanding Dissertation Award, USF