J. Das, S. M. Alam and S. Bhanja, "Ultra-low Power Hybrid CMOS-Magnetic LogicArchitecture", Accepted for IEEE Transactions on Circuits and Systems, 2012.
Abstract:
Magnetic coupling between single layer nanomagnets is
used to realize magnetic logic. Apart from writing and reading,
one other phenomenon performed on the magnets is
clocking. Traditionally, these operations were carried out using
external magnetic fields generated by current carrying
conductors. But the current requirements are typically in mA
which increases the overall power. Also, the fields cannot be
sharply terminated at the boundary between two nanomagnets
which needs to be clocked at two different instants. The above
concerns motivated us to look into alternate magnetic devices
to realize magnetic logic. We suggested the use of multilayer
spintronic devices (the Magnetic Tunnel Junctions abbr.
MTJs) for carrying out logic computation. MTJs are already
in use in magnetic-MRAMs from where we have borrowed
some concepts in writing and reading our logic. The MTJ
free layers are capable of interacting with neighbors through
magnetic coupling. We have proposed the use of this coupling
to compute logic in this paper. At the same time, MTJs also
provide scope for CMOS integration which we have used
to assist in current driven writing, clocking and reading the
devices. CMOS integration also improves the overall control
over individual cells in the logic. In this paper we have
presented a novel CMOS integrated MTJ architecture layout
that enables (a) logic computation using magnetic coupling
between MTJs and (b) current driven input, clock and read
operations that are much more energy efficient. A feasibility
study of this integration in 22nm CMOS node is presented
in the paper along with a variability tolerant reading scheme
for the logic. The proposed architecture achieves over 95%
reduction in energy as seen in various adders and array multiplier
over traditional magnetic logic with external field-based
clocking.
Abstract:
Magnetic coupling between single layer nanomagnets is
used to realize magnetic logic. Apart from writing and reading,
one other phenomenon performed on the magnets is
clocking. Traditionally, these operations were carried out using
external magnetic fields generated by current carrying
conductors. But the current requirements are typically in mA
which increases the overall power. Also, the fields cannot be
sharply terminated at the boundary between two nanomagnets
which needs to be clocked at two different instants. The above
concerns motivated us to look into alternate magnetic devices
to realize magnetic logic. We suggested the use of multilayer
spintronic devices (the Magnetic Tunnel Junctions abbr.
MTJs) for carrying out logic computation. MTJs are already
in use in magnetic-MRAMs from where we have borrowed
some concepts in writing and reading our logic. The MTJ
free layers are capable of interacting with neighbors through
magnetic coupling. We have proposed the use of this coupling
to compute logic in this paper. At the same time, MTJs also
provide scope for CMOS integration which we have used
to assist in current driven writing, clocking and reading the
devices. CMOS integration also improves the overall control
over individual cells in the logic. In this paper we have
presented a novel CMOS integrated MTJ architecture layout
that enables (a) logic computation using magnetic coupling
between MTJs and (b) current driven input, clock and read
operations that are much more energy efficient. A feasibility
study of this integration in 22nm CMOS node is presented
in the paper along with a variability tolerant reading scheme
for the logic. The proposed architecture achieves over 95%
reduction in energy as seen in various adders and array multiplier
over traditional magnetic logic with external field-based
clocking.
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