Book Chapters

1.     J. Das, S. M. Alam and S. Bhanja, “STT-based Non-Volatile Logic-in-Memory Framework” in Field-Coupled Nanocomputing, edited by S. Bhanja and N. Anderson, LNCS Series (Springer).

2.     J. Pulecio, S. Sarkar and S. Bhanja, “An Experimental Demonstration of the Viability of Energy Minimizing Computing using Nano-magnets” in “Nanoelectronic Device Applications Handbook”, edited by James Morris & Krzysztof Iniewski, CRC Press (Taylor & Francis Group), 2012.

3.     J. Das, S. M. Alam and S. Bhanja, “Non-volatile Logic-in-Memory Architecture: An Integration between Nanomagnetic Logic and Magneto-resistive RAM” in “Nanoelectronic Device Applications Handbook”, edited by James Morris & Krzysztof Iniewski, CRC Press (Taylor & Francis Group), 2012.

4.     S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi, “QCA Circuits for Robust Coplanar Crossing”, in “Test, Defect Tolerance and Reliability for Emerging Nanotechnologies”, edited by Mohammad Tehranipoor, Springer Science +Business Media, LLC, 2008.

5.     S. Bhanja and N. Ranganathan, “Hardware Implementation of Data Compression”, in“Lossless Compression Handbook,” edited by K. Saud, Computer Society Press, 2002

Books and Special Issues

1.     K. A. Roxy and S. Bhanja, Non-Boolean Computing with Spintronic Devices. Foundations and Trends® in Electronic Design Automation, 12(1), 1-123, 2018.

2.     N. G. Anderson and S. Bhanja. Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives, Theoretical Computer Science and General Issues Series, Springer, ISBN 978-3-662-43722-3, 2014.

3.     Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies, ACM Journal of Emerging Technologies, Editors: A. Todri-Sanial and S. Bhanja, in print 2016.

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Education-related Publications (Journal and Conference)

1.      A. Hoque, W. Sutton, K. A. Roxy and S. Bhanja, "Integrating emerging memory technologies into undergraduate logic design course: The impact of context based teaching," 2017 IEEE International Conference on Microelectronic Systems Education (MSE), Lake Louise, AB, 2017, pp. 31-34.

2.      J. Das, and S. Bhanja, “A Novel Knowledge Module to Integrate Threshold Logic and Post-CMOS Technology into Undergraduate Logic Design Classroom" in IEEE Interdisciplinary Engineering Education Conference (IEDEC), pp. 24-30, March 2014.

3.      C. Siyambalapitiya, R. Hyde, K. Kusmierek  and S.Bhanja, “Effectiveness of Knowledge Module on “Intel 45 nm Transistor and High-k Dielectric”
into Undergraduate Semiconductor Devices Course”, in IEEE 2^nd Interdisciplinary Engineering Design Education Conference (IEDEC),  pp. 83 – 87, 2011.

4.       D. Karunaratne, S. Rajaram, P. De, K. Kusmierek  and S. Bhanja, “Novel knowledge module on fusion of logic and memory to undergraduate students”, in IEEE Microelectronic System Education Conference, pp. 64-67, 2011.

5.        J. Pulecio, A. Pulecio, M. Westlake and S. Bhanja, “A Snapshot of Young America’s Perspective towards STEM”, in IEEE Frontiers in Education (FIE),  pp. S2E-1 – S2E-2, 2010.

6.        K. Lingasubramanian and S. Bhanja, " Work In Progress - An Education Module on Engineering Ethics Concentrating on Environment-Friendly Engineering for Computer Engineers", in IEEE Frontiers in Education (FIE),  pp.  903-904, 2009.

7.        A. Kumari and S. Bhanja, "CNT logic knowledge module integrated in digital CMOS logic design", in IEEE Microelectronics Semiconductor Education,  pp. 115-117, 2009.

8.        S. Srivastava and S. Bhanja, “Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course”, in IEEE Transactions on Education, vol. 51(3), pp. 349-355, 2008.

9.        S. Srivastava and S. Bhanja, “WIP- Introduction of K-map based Nano-logic Synthesis in Logic Design Course”, in 37^th ASEE/IEEE Frontiers in Education (FIE), pp. S1C, 2007.

10.     S. Srivastava and S. Bhanja, "Knowledge Module for Logic Design to Introduce Majority Logic Synthesis Using Karnaugh Maps", in IEEE/ACM Intl. Conference on Microelectronic Systems Education (MSE), pp. 55-56, 2007.

11.     S. Bhanja, “WIP: Enhancing Performance using Dominant Sensory Mode in Co-opeartive Learning Environment for VLSI Design Courses”, IEEE Frontiers in  Education (FIE), pp. 14-15, October, 2007.

Conference papers (peer reviewed)

1.       K. A. Roxy and S. Bhanja, "Variability tolerant reading of nanomagnetic energy minimizing co-processor," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, 2017, pp. 413-416.

2.       K. A. Roxy and S. Bhanja, "Exploring the readability of nano-magnetic energy minimizing co-processor," 2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO), Pittsburgh, PA, 2017, pp. 1019-1022.

3.       I. B. Adames, J. Das, and S. Bhanja. "Survey of Emerging Technology Based Physical Unclonable Functions." In Proceedings of the 26th edition on Great Lakes Symposium on VLSI, pp. 317-322. ACM, 2016.

4.       G. Turvani, M. Bollo, J. Das, S. Bhanja, M. Graziano, M. Zamboni, , “Design of NML Circuits based on M-RAM”,  in IEEE Conference on Nanotechnology, 2015.

5.       J. Das, K. Scott, D. Burgett, S. Rajaram and S. Bhanja, “A Novel Geometry Based MRAM PUF” in IEEE Conference on Nanotechnology, pp. 859-863, 2014.

6.       J. Das, S. M. Alam, and S. Bhanja, “Prospects For Pipeline in High-Density Magnetic Field-Coupled Logic” in IEEE Conference on Nanotechnology, pp. 951-955, 2014.

7.       R. Panchumarthy, D.K Karunaratne, S. Sarkar, and S. Bhanja, “Magnetic State Estimator to Characterize the Magnetic States of Nano-Magnetic Disks”, AIP Magnetism and Magnetic Materials Conference MMM, 2013.

8.       S. Rajaram, D. K. Karunaratne, S. Sarkar, S. Bhanja, “Study of Dipolar Neighbor Interaction on Magnetization States of Nano-Magnetic Disks”, AIP Magnetism and Magnetic Materials Conference MMM, 2013.

9.       J. Das, S. M. Alam and S. Bhanja, “Non-Destructive Variability Tolerant Differential Read for Non-Volatile Logic”, in IEEE 55th Int'l Midwest Symposium on Circuits & Systems, pp.178-181, 2012.

10.    S. Mishra and S. Bhanja, “Evaluation of Circuit Styles and VLSI Logic Designs of Pentacene OTFTs”, in IEEE 55th Int'l Midwest Symposium on Circuits & Systems, pp. 121-124, 2012.

11.    J. Das, S. M. Alam and S. Bhanja, “Addressing The Layout Constraint Problem in Cascading Logic Gates in Nanomagnetic Logic”, in IEEE Conference on Nanotechnology,  pp. 1-4, 2012.

12.    J. Das, S. M. Alam and S. Bhanja, “A Novel Design Concept for High Density Hybrid CMOS-Nanomagnetic Circuits”, in IEEE Conference on Nanotechnology, pp. 1-6, 2012.

13.    S. Rajaram, D. Karunaratne and S. Bhanja, “Study of Multilayer Spintronic Devices for Logic Computation”, in IEEE INTERMAG, 2012.

14.    M. Puri and S. Bhanja, “13,6-N-sulfinylacetamidopentacene based Fully Encapsulated Low Voltage Vertical Short Channel OFET”, in OSA Solid-State and Organic Lighting (SOLED), November 2011.

15.    J. Das, S. M. Alam, S. Rajaram and S. Bhanja, “Hybrid CMOS-MQCA Architecture using Multi-layer Spintronic Devices, WIP, IEEE/ACM Design Automation Conference (DAC), 2011.

16.    D. K Karunaratne and S. Bhanja, “Programmable logic system for Magnetic Cellular Automata”, in AIP Magnetism and Magnetic Materials Conference MMM, 2011.

17.    S. Rajaram, S. Bhanja, “Boolean Logic Implementation using Coupled Spin Valves”, in AIP Magnetism and Magnetic Materials Conference MMM, 2011.

18.    J. Das, S. M. Alam and S. Bhanja, “Low Power CMOS-Magnetic Nano-Logic With Increased Bit Controllability”, in IEEE Conference on Nanotechnology, pp. 1261-1266, 2011.

19.    J. Pulecio, S. Sarkar and S. Bhanja, “Experimental Demonstration of Viability of Energy Minimizing Computing using Nano-magnets”, in IEEE Conference on Nanotechnology, pp. 1038-1042, 2011.

20.    D. Karunaratne, S. Rajaram, P. De, K. Kusmierek  and S. Bhanja, “Novel knowledge module on fusion of logic and memory to undergraduate students”, in IEEE Microelectronic System Education Conference, pp. 64-67, 2011.

21.    R. Panchumarthy, D. Karunaratne, S. Sarkar and S. Bhanja, “Tool for Analysis and Quantification of Fabrication Layouts in Nanomagnet-based Computing”, in IEEE Conference on Nanotechnology,  pp. 111-115, 2011.

22.    S. Bhanja and J. Pulecio, “A Review of Magnetic Cellular Automata Systems”, (Invited paper)  in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2373-2376, 2011.

23.    S. Srivastava, A. Asthana, S. Bhanja and S. Sarkar “QCAPro - An Error-Power Estimation Tool for QCA Circuit Design”, (Invited paper) in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2377-2380,  2011.

24.    D. Karunaratne, J. Pulecio and S. Bhanja, “Driving Magnetic Cells for Information Storage and Propagation”, in IEEE Nanotechnology Materials and Devices Conference, pp. 360-363, 2010.

25.    A. Kumari, S. Sarkar and S. Bhanja, “Study of Magnetization State Transition in Coupled Nanomagnet for Computation”, in IEEE/AIP Magnetism and Magnetic Materials Conference MMM-Intermag, 2010.

26.    J. Pulecio and S. Bhanja, "Magnetic Cellular Automata Coplanar Cross Wire Systems", in joint IEEE/AIP Magnetism and Magnetic Materials Conference, MMM-Intermag, 2010.

27.    J. Pulecio and S.Bhanja, "Magnetic Cellular Automata Coplanar Cross Wire Systems", in Nano-DDS (Platform paper), pp. 109, 2009.

28.    A. Kumari and S. Bhanja, “Magnetic Cellular Automata (MCA) Arrays under Spatially Varying Field”, (invited) in IEEE Nanotechnology Materials and Devices Conference,  pp. 50-53, 2009.

29.    J. Pulecio and S. Bhanja, “Magnetic Cellular Automata Wires”, in IEEE Nanotechnology Materials and Devices Conference,  pp. 73-75, 2009.

30.    A. Kumari, J. Pulecio and S. Bhanja, “Defect Characterization in Magnetic Field-Coupled Arrays”, in IEEE   Symposium on Quality of Electronic Design,  pp. 436-441, 2009.

31.    K. Lingasubramanian, S. Bhanja, "An Error Model to Study the Behavior of Transient Errors in Sequential Circuits," in IEEE International Conference  on VLSI Design, pp. 485-490, 2009.

32.    A. Shareef, K. Lingasubramanian and S. Bhanja, “Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits”, in IEEE Conference on Nanotechnology, pp. 895-898, Arlington, 2008.

33.    P. Venkataramani, S. Srivastava and S. Bhanja, “Sequential Circuit Design in Quantum-dot Cellular Automata”, in IEEE Conference on Nanotechnology, pp. 534-537, Arlington, 2008.

34.    S. Sarkar and S. Bhanja, “Direct Quadratic Minimization using Magnetic Field-based Computing”, in IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, pp. 31-34, 2008.

35.    S. Srivastava, S. Sarkar and S. Bhanja, “Error-Power Tradeoffs in QCA Design”, in IEEE Conference on Nanotechnology, pp. 530-533, Arlington, 2008.

36.    J. Pulecio and S. Bhanja, “Reliability of Bi-stable Single Domain Nano Magnets for Cellular Automata”, in IEEE Conference on Nanotechnology, pp. 782-786, Hong Kong, 2008.

37.    K. Lingasubramanian and S. Bhanja, “Probabilistic Maximum Error Modeling for Unreliable Logic Circuits”,  in ACM Great Lake Symposium on VLSI, pp. 223-226, 2007.

38.    S. Srivastava, S. Sarkar and S. Bhanja, “Power Dissipation Bounds and Models for Quantum-dot Cellular Automata Circuits”, in IEEE Conference on Nanotechnology, pp. 375-378, Cincinnati, 2006.

39.    S. Bhanja and S. Sarkar, “Switching Error Modes of QCA Circuits”, in IEEE Conference on Nanotechnology, pp. 383-386, Cincinnati, 2006.

40.    S. Srivastava and S. Bhanja, “Bayesian Macromodeling for Circuit Level QCA Design”, in IEEE Conference on Nanotechnology, pp. 31-34, Cincinnati, 2006.

41.    T. Rejimon and S. Bhanja, “Probabilistic Error Model for Unreliable Nano-Logic gates”, in IEEE Conference on Nanotechnology, pp. 47-50, Cincinnati, 2006.

42.    S. Bhanja, M. Ottavi, S. Pontarelli and F. Lombardi,  “Novel Designs for Thermally Robust Coplanar Crossing in QCA”, in IEEE Design Automation and Test in  Europe (DATE), vol. 1, pp. 6, 2006.

43.    T. Rejimon and S. Bhanja, “A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity”, in IEEE  International Conference on VLSI Design, issn 1063-9667, 2006 (Nominated for “Best Paper Award” and received “Honorable mention award”).

44.    T. Rejimon and S. Bhanja,  “Scalable Probabilistic Computing Models using Bayesian Networks”, in IEEE  International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 712-715,   2005.

45.    V. K. Jain, S. Bhanja, G. H. Chapman, L. Doddannagari and N. Nguyen, “A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous SoC”, IEEE SOC Conference, pp. 243-246, 2005.

46.    T. Rejimon, L. Hoffmann and S. Bhanja, “A Probabilistic Model for Single-Event-Upset”, in 12^th NASA Symposium on VLSI, 2005.

47.    S. Srivastava and S. Bhanja, “Hierarchical Bayesian Macromodeling for QCA Circuits”, in 12^th NASA Symposium on VLSI, 2005.

48.    S. Bhanja and  S. Sarkar, “Graphical Probabilistic Inference for Ground State and Near-Ground State Computing in QCA Circuits”, in IEEE Nanotechnology Conference, pp. 290-293, 2005.

49.    S. Sarkar and S. Bhanja, ”Synthesizing Energy Minimizing Quantum-dot Cellular Automata Circuits for Vision Computing”, in  IEEE Nanotechnology Conference, pp. 541-544, 2005.

50.    N. Ramalingam and S. Bhanja, “Causal Probabilistic Input Dependency Learning for Switching Model in VLSI Circuits”,  in ACM Great Lake Symposium on VLSI, pp. 112-115, 2005.

51.    S. Bhanja and S. Srivastava, “Bayesian Modeling of Quantum-dot Cellular Automata Circuits”, in Nanotech, National Science and Technology Institute, 2005.

52.    V. Jain, S. Bhanja, G. Chapman, L. Doddannagari and N. Nguyen, “A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor”, in IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. v/77- v/80, 2005.

53.    T. Rejimon and S. Bhanja,” An Accurate Probabilistic Model for Error Detection”, in 18^th IEEE International Conference in VLSI Design, pp.717-722, 2005.

54.    S. Bhanja, K. Lingasubramanian and N. Ranganathan, "Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks,” in 18^th IEEE International Conference in VLSI Design, pp. 586-591, 2005.

55.    S. Ramani and S. Bhanja, “Anytime Probabilistic Switching Model using Bayesian Networks,”   in IEEE International Symposium  on Low Power Electronic Design, pp. 86-89, 2004.

56.    S. Bhanja and N. Ranganathan,” Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams ”, in International Conference on Computer Design (ICCD), pp. 388-390, 2002.

57.    S. Bhanja and N. Ranganathan, “Accurate Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks”, in 15^th IEEE International Conference of VLSI Design & 7^th ASP-Design and Automation Conference, pp.  187-192, 2002.

58.    S. Bhanja and N. Ranganathan, “Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks,” in IEEE/ACM Design Automation Conference (DAC), pp. 209-214, 2001.

59.    S. Bhanja, M. Fletcher-Heath, L. O. Hall, D. B. Goldgof and J. P. Krischer, “A Qualitative Expert System for Clinical Trial Assignment”, in 11^th International Florida Artificial Intelligence, pp. 84-88, 1998.