A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor

V. Jain, S. Bhanja, G. Chapman, L. Doddannagari and N. Nguyen, “A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor”, Accepted for publication in IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.v77-v80, 2005.


@INPROCEEDINGS{1416244,
title={A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor},
author={Jain, V.K. and Bhanja, S. and Chapman, G.H. and Doddannagari, L. and Nguyen, N.},
booktitle={Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on},
year={2005},
month={March},
volume={5},
number={},
pages={ v/77-v/80 Vol. 5},
abstract={ A 3D heterogeneous sensor using a stacked chip has recently been proposed. While the sensors are located on one of the planes, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on its DSP plane, in particular on the implementation of the ICA (independent component analysis) algorithm in the DSP plane. ICA is a recently proposed method for solving the blind source separation problem. The objective is to recover the unobserved source signals from the observed mixtures without the knowledge of the mixing coefficients. We present a parallel architecture utilizing the reconfigurable J-platform, which employs coarse-gain VLSI cells. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the distinct advantages of reduced external interconnect, much reduced design time, and manageable testability. Additionally, the other algorithms needed for the 3D HSoC can also be mapped on to the same resources, by time multiplexing, thereby reducing the silicon area needed.},
keywords={ VLSI, blind source separation, digital signal processing chips, independent component analysis, parallel architectures, reconfigurable architectures, sensors, system-on-chip 3D HSoC, 3D heterogeneous sensor, ICA algorithm, blind source separation, coarse-gain VLSI cells, data-fabric cell, extended multiply accumulate cell, independent component analysis, parallel architecture, reconfigurable J-platform, sensor DSP plane, stacked chip sensor, time multiplexing, universal nonlinear cell},
doi={10.1109/ICASSP.2005.1416244},
ISSN={1520-6149}, }

An Accurate Probabilistic Model for Error Detection

T. Rejimon and S. Bhanja,” An Accurate Probabilistic Model for Error Detection”, 18th International Conference in VLSI Design, pp.717-722, 2005.


@INPROCEEDINGS{1383359,
title={An accurate probabilistic model for error detection},
author={Rejimon, T. and Bhanja, S.},
booktitle={VLSI Design, 2005. 18th International Conference on},
year={2005},
month={Jan.},
volume={},
number={},
pages={ 717-722},
abstract={We propose a novel single event fault/error model based on logic induced fault encoded directed acyclic graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in nanodomain logic block) that depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, we show that we are able to estimate detection probabilities of single-event faults/errors on IS-CAS'85 benchmarks with high accuracy (zero-error), linear space requirement complexity, and with an order of magnitude (≈5 times) reduction in estimation time over corresponding BDD based approaches.},
keywords={ belief networks, error detection, logic circuits, probabilistic logic Bayesian networks, IS-CAS'85 benchmark, LIFE-DAG, circuit logic, detection probability, error detection, error susceptibility, estimation time reduction, logic induced fault encoded directed acyclic graph, nanodomain logic block, probabilistic model, single event fault error model},
doi={10.1109/ICVD.2005.46},
ISSN={1063-9667 }, }

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks

S. Bhanja, K. Lingasubramanian and N. Ranganathan, "Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks,” 18^th International Conference in VLSI Design, pp.586-591, 2005.

@INPROCEEDINGS{1383338,
title={Estimation of switching activity in sequential circuits using dynamic Bayesian networks},
author={Bhanja, S. and Lingasubramanian, K. and Ranganathan, N.},
booktitle={VLSI Design, 2005. 18th International Conference on},
year={2005},
month={Jan.},
volume={},
number={},
pages={ 586-591},
abstract={ We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a dynamic Bayesian network. Dynamic Bayesian networks are extremely powerful in modeling high order temporal as well as spatial correlations; it is an exact model for the underlying conditional independencies. The attractive feature of this graphical representation of the joint probability function is that not only does it make the dependency relationships amongst the nodes explicit but it also serves as a computational mechanism for probabilistic inference. We report average errors in switching probability of 0.006, with errors tightly distributed around the mean error values, on IS-CAS'89 benchmark circuits involving up to 10000 signals.},
keywords={ belief networks, inference mechanisms, integrated circuit modelling, probability, sequential circuits, sequential switching, switching circuits IS-CAS'89, benchmark circuits, computational mechanism, dynamic Bayesian network, dynamic Bayesian networks, exact model, graphical representation, joint probability function, logic structure, nonsimulative probabilistic model, probabilistic inference, sequential circuits, spatiotemporal correlations, switching activity, switching probability, temporal dependency model},
doi={10.1109/ICVD.2005.93},
ISSN={1063-9667 }, }

Time and Space Efficient Method for Accurate Computation of Error Detection Probabilities

T. Rejimon and S. Bhanja, “Time and Space Efficient Method for Accurate Computation of Error Detection Probabilities”, IEE Proc. Computers & Digital Techniques, Volume 152, Issue 5, pp. 679 - 685 , 2005.


@ARTICLE{1532089,
title={Time and space efficient method for accurate computation of error detection probabilities in VLSI circuits},
author={Rejimon, T. and Bhanja, S.},
journal={Computers and Digital Techniques, IEE Proceedings -},
year={2005},
month={Sept.},
volume={152},
number={5},
pages={ 679-685},
abstract={The authors propose a novel fault/error model based on a graphical probabilistic framework. They arrive at the logic induced fault encoded directed acrylic graph (LIFE-DAG), which is proven to be a Bayesian network, capturing all spatial dependencies induced by the circuit logic. Bayesian networks are the minimal and exact representation of the joint probability distribution of the underlying probabilistic dependencies that not only use conditional independencies in modelling but also exploit them for achieving minimality and smart probabilistic inference. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in the nano-domain logic block) which depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, they show that they are able to estimate detection probabilities of faults/errors on ISCAS'85 benchmarks with high accuracy, linear space requirement complexity, and with an order of magnitude (≈5 times) reduction in estimation time over corresponding binary decision diagram based approaches.},
keywords={ VLSI, computational complexity, directed graphs, error detection, inference mechanisms, integrated circuit modelling, logic design, statistical distributions BDD based approach, Bayesian network, LIFE-DAG, VLSI circuits, accurate computation, circuit logic, error detection probabilities, error model, estimation time reduction, exact representation, fault model, graphical probabilistic framework, linear space requirement complexity, logic induced fault encoded directed acrylic graph, minimal representation, probabilistic inference, probability distribution, soft error susceptibility, space efficient method, time efficient method},
doi={10.1049/ip-cdt:20045106},
ISSN={1350-2387}, }

Anytime Probabilistic Switching Model using Bayesian Networks

S. Ramani and S. Bhanja, “Anytime Probabilistic Switching Model using Bayesian Networks,” International Symposium on Low Power Electronic Design, pp 86-89, 2004.

@INPROCEEDINGS{1349315,
title={Any-time probabilistic switching model using Bayesian networks},
author={ Ramani, S.S. and Bhanja, S.},
booktitle={Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on},
year={2004},
month={Aug.},
volume={},
number={},
pages={ 86-89},
abstract={ Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian network based switching model can explicitly model all spatio-temporal dependency relationships in a combinational circuit, resulting in zero-error estimates. However, the space-time requirements of exact estimation schemes, based on this model, increase with circuit complexity. This paper explores a non-simulative, importance sampling based, probabilistic estimation strategy that scales well with circuit complexity. It has the any-time aspect of simulation and the input pattern independence of probabilistic models.},
keywords={ belief networks, circuit complexity, combinational circuits, combinational switching, importance sampling, probabilistic logic, probability ISCAS circuits, anytime probabilistic switching model, circuit complexity, combinational circuits, gate level switching activity, importance sampling, input pattern independence, joint probability distribution function, logic level switching activity, low-power design, probabilistic Bayesian network, spatiotemporal dependency relationships, stochastic inference},
doi={10.1109/LPE.2004.1349315},
ISSN={ }, }

Cascaded Bayesian Inferencing for Switching Activity Estimation with Correlated Inputs

S. Bhanja and N. Ranganathan, “Cascaded Bayesian Inferencing for Switching Activity Estimation with Correlated Inputs,” IEEE Transaction on VLSI Systems, Volume 12, Issue 12, pp .1360 – 1370, 2004.


@ARTICLE{1407954,
title={Cascaded Bayesian inferencing for switching activity estimation with correlated inputs},
author={Bhanja, S. and Ranganathan, N.},
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
year={2004},
month={Dec},
volume={12},
number={12},
pages={ 1360-1370},
abstract={ In this paper, we investigate the estimation of switching activity in VLSI circuits using a graphical probabilistic model based on cascaded Bayesian networks (CBNs). First, we develop a theoretical analysis for Bayesian inferencing of switching activity and then derive upper bounds for certain circuit parameters which, in turn, are useful in establishing the cascade structure of the CBN model. We formulate an elegant framework for maintaining probabilistic consistency in the interfacing boundaries across the CBNs during the inference process using a tree-dependent (TD) probability distribution function. A TD distribution is an approximation of the true joint probability function over the switching variables, with the constraint that the underlying BN representation is a tree. The tree approximation of the true joint probability function can be arrived at by using a maximum weight spanning tree (MWST) built using pairwise mutual information about the switching occurring at pairs of signal lines on the boundary. Further, we show that the proposed TD distribution function can be used to model correlations among the primary inputs which is critical for accuracy in modeling of switching activity. Experimental results for ISCAS circuits are presented to illustrate the efficacy of the proposed CBN models.},
keywords={ Bayes methods, VLSI, approximation theory, belief networks, boundary-value problems, cascade networks, circuit complexity, circuit switching, electronic engineering computing, estimation theory, inference mechanisms, statistical analysis, statistical distributions, trees (mathematics) ISCAS circuits, VLSI circuits, cascaded Bayesian inference methods, cascaded Bayesian networks, circuit complexity, circuit parameters, correlation inputs, graphical probabilistic model, maximum weight spanning tree, pairwise mutual information, probability distribution function, switching activity estimation, switching activity modeling, switching variables, tree approximation, tree dependent distribution, true joint probability function, upper bounds},
doi={10.1109/TVLSI.2004.837991},
ISSN={1063-8210}, }

Switching activity estimation of VLSI circuits using Bayesian networks

S. Bhanja and N. Ranganathan,“Switching Activity Estimation of VLSI Circuits using Bayesian Networks,” IEEE Transactions on VLSI Systems,
pp. 558- 567, Feb. 2003.


@ARTICLE{1229864,

 title={Switching activity estimation of VLSI circuits using Bayesian networks},
 author={Bhanja, S. and Ranganathan, N.},
 journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
 year={2003},
 month={Aug.},
 volume={11},
 number={4},
 pages={ 558-567},
 abstract={ Switching activity estimation is an important aspect of
power estimation at circuit level. Switching activity in a node is
temporally correlated with its previous value and is spatially
correlated with other nodes in the circuit. It is important to capture
the effects of such correlations while estimating the switching
activity of a circuit. In this paper, we propose a new switching
probability model for combinational circuits that uses a logic-induced
directed-acyclic graph (LIDAG) and prove that such a graph corresponds
to a Bayesian network (BN), which is guaranteed to map all the
dependencies inherent in the circuit. BNs can be used to effectively
model complex conditional dependencies over a set of random variables.
The BN inference schemes serve as a computational mechanism that
transforms the LIDAG into a junction tree of cliques to allow for
probability propagation by local message passing. The proposed approach
is accurate and fast. Switching activity estimation of ISCAS and MCNC
circuits with random and biased input streams yield high accuracy
(average mean error=0.002) and low computational time (average elapsed
time including CPU, memory access and I/O time for the benchmark
circuits=3.93 s).},

keywords={ VLSI, belief networks, directed graphs, integrated
circuit modelling, logic simulation, probability Bayesian network,
Bayesian networks, ISCAS circuits, LIDAG, MCNC circuits, VLSI circuits,
computational mechanism, computational time, conditional dependencies,
junction tree, local message passing, logic-induced directed acyclic
graph, power estimation, probability propagation, switching activity
estimation, switching probability model},

doi={10.1109/TVLSI.2003.816144},
ISSN={1063-8210},
}